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Computer Engineering II 4 th year, Communications Engineering Winter 2014 Lec. # 3 Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.

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Presentation on theme: "Computer Engineering II 4 th year, Communications Engineering Winter 2014 Lec. # 3 Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering."— Presentation transcript:

1 Computer Engineering II 4 th year, Communications Engineering Winter 2014 Lec. # 3 Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering

2 Course Web Page Email:

3 Lecture 3 Chapter 5. Internal Memory Technology (Cont.)

4 0 1 1 0 0 1 0 A B C Discrepancies Hamming SEC-DED Code 0 1 Fix error 1 Wrong!!!

5 0 1 1 0 0 1 0 A B C Discrepancies Hamming SEC-DED Code (2) 0 1 Fix error 1 11 ×

6 Increase in Word Length with Error Correction

7 Advanced DRAM Organization Interface to main memory is a system bottleneck. DRAM chip is the main building block of MM. Basic DRAM architecture same since 1970s. DRAM chip is constrained by its internal architecture and its interface to CPU’s MM bus. Enhancements to basic DRAM architecture —SDRAM —DDR-DRAM —RDRAM —CDRAM

8 Synchronous DRAM (SDRAM) Traditional DRAM is asynchronous. SDRAM exchanges data with CPU synchronized to an external clock (system bus). No wait states! —SDRAM moves data in and out under control of system clock. —CPU issues instruction and address. —Latched by the SDRAM. —SDRAM responds after a number of clock cycles. —Meanwhile, CPU can do other tasks  no waits.

9 Synchronous DRAM (SDRAM) (2) Burst mode: a series of data bits can be clocked out rapidly after the first bit has been accessed. Eliminates row and column address setup time. Useful when the required bits are in sequence and in the same row of the array as the initial access. Multiple-bank internal architecture improves opportunities for parallelism. Mode Register (MR) —Specifies burst length. —Allows programmer to adjust latency between read request and data transfer. Double Data Rate (DDR-SDRAM) sends data to CPU twice per clock cycle (leading & trailing edges).


11 SDRAM Operation Burst length: 4 Latency: 2 Burst read command is initiated by: CS and CAS low and RAS and WE high at the rising edge of the clock. Address determines the starting column for the burst.

12 Rambus DRAM (RDRAM) Adopted by Intel for Pentium & Itanium. Main competitor to SDRAM. Vertical package – all pins on one side. Data exchange over 28 wires < 12 cm long. Bus addresses up to 320 RDRAM chips at 1.6 Gbps. Asynchronous block-oriented protocol — Initial 480 ns access time. — Then 1.6 Gbps What makes this speed possible is the bus itself, which defines impedances, clocking, and signals very precisely. RDRAM gets a memory request over the high- speed bus. This request contains address, operation, number of bytes.

13 RDRAM Diagram Controller and a number of RDRAM modules connected via a common bus. Bus: 18 data lines, cycling at twice the clock rate  800 Mbps. Address and control signals: 8 lines (RC) Clock starts at the far end from the controller, propagates to the controller end, then loops back. Module sends data to the controller synchronously to the clock to master. Controller sends data to a module synchronously with the clock in the opposite direction.

14 Cache DRAM (CDRAM) Small SRAM cache (16 kb) onto DRAM chip. Can be used as a true cache with 64-bit lines. Can be used as a buffer to support the serial access of a block of data. e. g., to refresh a bit-mapped screen, the CDRAM can prefetch the data from the DRAM into the SRAM buffer. Subsequent accesses to the chip results in accesses to the SRAM only.

15 Chapter 6. External Memory

16 Types of External Memory Magnetic Disk —RAID —Removable Optical —CD-ROM —CD-Recordable (CD-R) —CD-R/W —DVD Magnetic Tape Not Semi-Conductors

17 Magnetic Disk Foundation of external memory on computers. Disk substrate: circular platter constructed of nonmagnetic material. Substrate coated with magnetizable material (iron oxide). Substrate used to be aluminium or aluminium alloy. Now glass ... —Improved surface uniformity  more reliability. —Reduction in surface defects  less read/write errors. —Ability to support lower flight heights (see later). —Better stiffness to reduce disk dynamics. —Better shock/damage resistance.

18 Read and Write Mechanisms Head: Small device (conductive coil) that can read from or write to a portion of the platter rotating under it. May be single read/write head or separate ones. During read/write, head is stationary, platter rotates. Write —FACT: Current through coil produces magnetic field. Current direction. —Pulses sent to head. —Magnetic pattern recorded on surface below. Read (traditional) - floppy and old disks —FACT: Magnetic field moving relative to a coil produces current in the coil. —Coil is the same for read and write  one read/write head. Read (contemporary) —Separate read head, close to write head. —Partially shielded magnetoresistive (MR) sensor. —Electrical resistance depends on direction of magnetic field. —Current is passed thru the MR and resistance is read as voltage. —High frequency operation  Greater storage density and operating speed.

19 Inductive Write MR Read

20 Disk Data Layout

21 Data Organization and Formatting Tracks: concentric rings —Track’s width = head’s width. —Intertrack gaps between adjacent tracks  prevent errors due to misalignment of the head or interference. —Reduce gap to increase capacity. —Same number of bits per track (variable packing density). —Constant angular velocity. Sectors: tracks are divided into sectors. —Fixed (512 bytes) or variable length. —Hundreds per track. —Intersector gaps. Block: minimum # of sectors that can be read from or written into the disk at a time. Block size ≥ one sector.

22 Disk Velocity  Disk Layout Bit near center of rotating disk passes fixed point slower than bit on outside of disk. Head must read all bits in the same rate  increase spacing between bits in different tracks. CAV: Rotate disk at a Constant Angular Velocity —Gives pie shaped sectors and concentric tracks. —Individual blocks directly addressed by track and sector. —Move head to a given track and wait for a given sector. —Waste of space on outer tracks  lower data density. Multiple zone recording: use zones to increase capacity —Each zone has a fixed number of bits per track. —More complex circuitry.

23 Finding Sectors Must be able to identify start of track and sector. Format disk —Extra control data recorded on the disk to marks tracks and sectors. —Used only by the disk drives, not accessible to the user. Seagate ST506 format

24 Reading Material Stallings, chapter 5, pages 173-177, 179. Stallings, chapter 6, pages 184-188.

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