1. - Faculty of Engineering Integrated Circuits Laboratory 28-June-2003 Integrated RF Receivers Design Issues Presented by: Sameh Assem Ibrahim

2. - 2/24 Faculty of Engineering Integrated Circuits Laboratory Outline RF Receiver ArchitecturesRF Receiver Architectures The Proposed ArchitectureThe Proposed Architecture Image RejectionImage Rejection Sensitivity to Process VariationsSensitivity to Process Variations ReferencesReferences

3. - Faculty of Engineering Integrated Circuits Laboratory 28-June-2003 RF Receiver Architectures

4. - 4/24 Faculty of Engineering Integrated Circuits Laboratory Super-Heterodyne Receiver RF Receiver Architectures Block Diagram

5. - 5/24 Faculty of Engineering Integrated Circuits Laboratory Super-Heterodyne Receiver High selectivity High selectivity High sensitivity High sensitivity Most widely used in discrete implementations Most widely used in discrete implementations  Difficult to integrate  Very high Q filters are required RF Receiver Architectures Advantages and Disadvantages

6. - 6/24 Faculty of Engineering Integrated Circuits Laboratory Homodyne Receiver RF Receiver Architectures Block Diagram

7. - 7/24 Faculty of Engineering Integrated Circuits Laboratory Homodyne Receiver High integratability High integratability No need for high image rejection ratios No need for high image rejection ratios  DC offsets  Back radiation  High flicker noise  Need for high I-Q matching accuracy RF Receiver Architectures Advantages and Disadvantages

8. - 8/24 Faculty of Engineering Integrated Circuits Laboratory RF Receiver Architectures Low-IF Receiver Block Diagram

9. - 9/24 Faculty of Engineering Integrated Circuits Laboratory Low-IF Receiver High integratability High integratability No DC offset problems No DC offset problems No flicker noise No flicker noise The best candidate for modern integrated receivers The best candidate for modern integrated receivers  Need for high I-Q matching accuracy RF Receiver Architectures Advantages and Disadvantages

10. - Faculty of Engineering Integrated Circuits Laboratory 28-June-2003 Image Rejection

11. - 11/24 Faculty of Engineering Integrated Circuits Laboratory The Choice of IF Precaution 1 Image Rejection I PP PPF Notch Filter PP Divider Image-reject PLL Q LNA LO f rf f lo1 f lo2 f if =f rf -(f lo1 +f lo2 ) f image =2(f lo1 +f lo2 )- f rf f rf f lo1 +f lo2 f if f image f rf f lo1 +f lo2 f if f image

12. - 12/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Filters Image Rejection Precaution 2 Real Signals: f f LO -f LO f rf f im -f im -f rf f f if -f if f

13. - 13/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Filters Image Rejection Precaution 2 Complex Signals: f -f LO f rf f im -f im -f rf f f if -f if f

14. - 14/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Filters Image Rejection Precaution 2 f if -f if f f if -f if f Active Polyphase Filter Bandpass filter Preferred at low frequencies Can be used for channel selection Passive Polyphase Filter Bandstop filter Preferred at high frequencies

15. - 15/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Filters Image Rejection Precaution 2 I PP PPF Notch Filter PP Divider Image-reject PLL Q LNA LO PassiveActive

16. - 16/24 Faculty of Engineering Integrated Circuits Laboratory LNA with a Notch Filter [6] Precaution 3 Image Rejection

17. - Faculty of Engineering Integrated Circuits Laboratory 28-June-2003 Sensitivity to Process Variations

18. - 18/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Filters Sensitivity to Process Variations Precaution 1 Sensitivity analysis for passive polyphase filters [9]

19. - 19/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Filters Sensitivity to Process Variations Precaution 1 Sensitivity analysis for active polyphase filters

20. - 20/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Polyphase Quadrature Generators Sensitivity to Process Variations Precaution 2 I PP PPF Notch Filter PP Divider Image-reject PLL Q LNA LO

21. - 21/24 Faculty of Engineering Integrated Circuits Laboratory Sensitivity to Process Variations Precaution 2 The Use of Polyphase Quadrature Generators Sensitivity analysis for polyphase quadrature generators [9]

22. - 22/24 Faculty of Engineering Integrated Circuits Laboratory The Use of Double Quadrature Down Conversion (DQDC) [7] Sensitivity to Process Variations Precaution 3 I PP PPF Notch Filter PP Divider Image-reject PLL Q LNA LO

23. - 23/24 Faculty of Engineering Integrated Circuits Laboratory Sensitivity to Process Variations Precaution 3 The Use of Double Quadrature Down Conversion (DQDC) [7] SQDC More affected by quadrature inaccuracy DQDC Less affected by quadrature inaccuracy Example: to reach 60 dB IRR 3% quadrature accuracy is enough for DQDC whereas 0.1 % is required for SQDC

24. - 24/24 Faculty of Engineering Integrated Circuits Laboratory References 1. A. A. Abidi, "Direct conversion radio transceivers for digital communications," IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995. 2. J. Crols and M. Steyaert, "A single-chip 900-MHz CMOS receiver front-end with a high-performance low-IF topology," IEEE J. Solid-State Circuits, vol. 32, pp. 1935-1950, Dec. 1997. 3. S. Jantzi and Adel S. Sedra, " Quadrature bandpass ΔΣ modulation for digital radio," IEEE J. Solid- State Circuits, vol. 30, pp. 1483-1492, Dec. 1995. 4. J. Rudell and P. Gray, "A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications," IEEE J. Solid-State Circuits, vol. 32, pp. 2071-2088, Dec. 1997. 5. S. Tadjpour and A. Abidi, "A 900 MHz dual conversion low-IF GSM receiver in 0.35 µm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1992-2002, Dec. 2001. 6. H. Rategh and T. Lee, " 5-GHz CMOS wireless LANs," IEEE Transactions on Microwave Theory and Techniques, vol. 50, pp. 268-280, Jan. 2002. 7. F. Behbahani and A. Abidi, "CMOS mixers and polyphase filters for large image rejection," IEEE J. Solid-State Circuits, vol. 36, pp. 873-887, June 2001. 8. J. Crols and M. Steyaert, “ CMOS wireless transceiver design”, Kluwer Academic Publishers, 1997 9. S. Galal, “A new front-end architecture for RF single chip communication transcievers”, a thesis for masters degree, 1999