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Slide 1 of 26ESA AMICSA 2006 Analogue and Mixed-Signal Systems Modelling for Space Communications presented by Dr. Rajan Bedi

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Presentation on theme: "Slide 1 of 26ESA AMICSA 2006 Analogue and Mixed-Signal Systems Modelling for Space Communications presented by Dr. Rajan Bedi"— Presentation transcript:

1 Slide 1 of 26ESA AMICSA 2006 Analogue and Mixed-Signal Systems Modelling for Space Communications presented by Dr. Rajan Bedi

2 Slide 2 of 26 ESA AMICSA 2006 Analogue and Mixed-Signal Systems Modelling for Space Communications UK EXPORT CONTROL SYSTEM EQUIPMENT & COMPONENTS RATING: 3A001a1a, 3A001a2, 3A001a5a1, 3A001a5a2, 3A001a5a3, 3A001a5a4, 3A001a5b, 3A101a, 3C001a, 3C001b, 4A002b2, 4A002b1 & 5E001c1. UK EXPORT CONTROL TECHNOLOGY RATING: 3E001, 4E001 5E001b1 & 5E001c2e. Rated By : Rajan Bedi with reference to UK Export Control Lists (version INTR_A12. DOC 13 August 2003) which contains the following caveat: “The control texts reproduced in this guide are for information purposes only and have no force in law. Please note that where legal advice is required, exporters should make their own arrangements”. Export licence : Not required for EU countries. Community General Export authorisation EU001 is valid for export to : Australia, Canada, Japan, New Zealand, Norway, Switzerland & USA.

3 Slide 3 of 26 ESA AMICSA 2006 Presentation Overview  Introduction  Motivation for Mixed-Signal Systems Modelling  Development of Mixed-Signal Simulation Environment  Capability of Mixed-Signal Simulation Environment  Simulation Results  Conclusion

4 Slide 4 of 26 ESA AMICSA 2006 Introduction  Telecommunication satellites with on-board digital processors require: –ADCs to digitize the IF/baseband uplink carrier in the receive section. –DACs to reconstruct the IF/baseband downlink carrier in the transmit section.  The specification of the ADCs/DACs are key to the success of a payload.  Parameters such as resolution, linearity and bandwidth limit the useful dynamic range of ADCs/DACs and ultimately that of the payload.

5 Slide 5 of 26 ESA AMICSA 2006 Motivation  Astrium wanted the capability to carry out detailed systems modelling of ADC and DAC devices.  We wanted to be able to predict how the ADC/DAC d.c. static errors, e.g. DNL, INL, offset and gain errors, affect converter performance and how this impacts overall payload performance.  We wanted to be able to predict how typical flight-hardware conditions affect converter performance and how this impacts overall payload performance, e.g. cycle-to-cycle jitter on the sampling clock and thermal noise on the ADC input. We wanted to be able to predict the interaction between the front-end analogue signal processing and the ADC, e.g. how anti-aliasing filters and amplifier non-linearities affect the performance of an ADC and the overall payload.

6 Slide 6 of 26 ESA AMICSA 2006 Motivation  The knowledge gained from this mixed-signal systems modelling will be used: To influence the specification and sourcing of ADC/DAC devices that can be used on future payloads. Satellite manufacturers have access to a very limited range of space-grade, mixed-signal converters – we have to get our selection right! To prevent unnecessary under-design or over-specification. To identify the limits to which circuit functionality and payload performance can be guaranteed in terms of ADC/DAC linearity, resolution and bandwidth. To understand how non-ideal ADC/DAC devices impact the overall system error budget and how this will affect the performance of a telecommunications satellite payload. To investigate optimal payload architectures based around ADCs/DACs for consideration on future missions.

7 Slide 7 of 26 ESA AMICSA 2006 Development of Mixed-Signal Simulation Environment  Following a review of commercially available EDA tools in early 2003, none existed that would allow extensive mixed- signal systems analyses.  In early 2003, work began on developing a simulation environment using the analogue and mixed-signal extensions to the VHDL language.  The simulation models were implemented using the VHDL- AMS mixed-signal hardware description language as part of a modern SOC design flow.  The simulation environment requires Mentor Graphics’s analogue and mixed-signal simulator - ADMS.  Mentor Graphics’s ADMS allows designs to be structured using a combination of VHDL-AMS, Verilog-A, SPICE, VHDL and Verilog using a single execution kernel.

8 Slide 8 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment  Behavioural, parameterisable ADC/DAC simulation models were developed that allow control over the following parameters: –d.c. static errors, i.e. DNL, INL, offset & gain errors (values taken directly from manufacturers data sheet) –ADC/DAC Resolution –ADC analogue full-scale input voltage range –ADC analogue input amplitude –ADC analogue input bandwidth –ADC/DAC input frequency –ADC/DAC sampling frequency –Jitter/phase noise on the ADC/DAC sampling clock –Unwanted interference (thermal noise) on the ADC analogue input.

9 Slide 9 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment  A very comprehensive VHDL-AMS testbench has been developed that automates single, two, four and eight-tone sinusoidal testing of the ADC/DAC simulation models.  The testbench also allows noise power ratio (NPR) testing of the ADC/DAC simulation models.  NPR testing allows satellite manufacturers to assess performance of an ADC/DAC using an input test signal representative of the traffic the converters will encounter in- flight.  NPR testing emulates a multi-carrier input signal by loading the ADC/DAC with GWN – it’s the true worst-case measurement for space communications!  NPR testing accounts for the intermodulation distortion among the input frequencies generated by the non-linear ADC/DAC device.  Only one known mixed-signal vendor reports an NPR metric on their datasheet – that’s for a DAC!

10 Slide 10 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment ADC Sinusoidal Testing ADC DUT FFT Sampling Clock Generator (normal/jitter) After the desired number of ADC conversions, the digitized ADC output is converted to the frequency domain for analysis.

11 Slide 11 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment DAC Sinusoidal Testing DAC DUT Perfect Quantizer Perfect Quantizer FFT Sampling Clock Generator (normal/jitter) A perfect quantizer is used to drive the DAC DUT. The analogue output is digitized by another perfect quantizer.

12 Slide 12 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment  Following ADC/DAC conversion, the frequency spectrum of the output is evaluated to assess the dynamic performance of the ADC/DAC simulation model.  The following performance metrics are reported:  SNR (Signal-to-Noise Ratio)  SINAD, and distortion ratio (SINAD)  Effective number of bits (ENOB)  Spurious-free dynamic range (SFDR)  Total harmonic distortion (THD)  Intermodulation distortion (IMD)  Noise Power Ratio  Dynamic range  Dynamic range violations, missing codes and any incidents of clipping are also reported.

13 Slide 13 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment ADC NPR Testing ADC DUT FFT Sampling Clock Generator Notch Filter Low-Pass Filter

14 Slide 14 of 26 ESA AMICSA 2006 Simulation Results Single-tone testing of an ADC simulation model based on the space-grade ADC flown on the Inmarsat 4 payload. SFDR = 77.9 dBc, SNR = 64.9 dB, ENOB = 10.5 bits, DR = 98.0 dB. Vendor datasheet reports an SFDR of 80 dBc and an SNR of 67 dB.

15 Slide 15 of 26 ESA AMICSA 2006 Simulation Results Two-tone testing of an ADC simulation model based on the space-grade ADC flown on the Inmarsat 4 payload. SFDR = 80.5 dBc, SINAD = 60.6 dB, ENOB = 9.7 bits, DR = 92.2 dB.

16 Slide 16 of 26 ESA AMICSA 2006 Simulation Results Four-tone testing of an ADC simulation model based on the space-grade ADC flown on the Inmarsat 4 payload. SFDR = 77.5 dBc, SINAD = 54.1 dB, ENOB = 8.69 bits, DR = 87.2 dB.

17 Slide 17 of 26 ESA AMICSA 2006 Simulation Results Eight-tone testing of an ADC simulation model based on the space-grade ADC flown on the Inmarsat 4 payload. SFDR = 70.3 dBc, SINAD = 46.0 dB, ENOB = 7.37 bits, DR = 79.2 dB. SFDR = 90.3 dBFS, Vendor datasheet reports an SFDR of 90 dBFS.

18 Slide 18 of 26 ESA AMICSA 2006 Simulation Results NPR testing of a DAC simulation model based on the space-grade DAC flown on the Inmarsat 4 payload and to be flown on the Galileo payload. The measured NPR is 47.1 dB (ENOB ~ 9.4 bits) after five iterations.

19 Slide 19 of 26 ESA AMICSA 2006 Simulation Results Sinusoidal testing of a DAC simulation model based on the space-grade DAC flown on the Inmarsat 4 payload and to be flown on the Galileo payload. SFDR = 69.9 dB, SNR =55.4 dB, ENOB = 8.9 bits, DR = 82.5 dB. Simulation environment reports a wideband SFDR around 70 dBc (no jitter on sampling clock). Vendor datasheet reports an SFDR of 66 dBc.

20 Slide 20 of 26 ESA AMICSA 2006 NPR Simulation Results from a Broadband Space-Grade ADC. The measured antilog-average-log NPR after ten simulations is 40.2 dB, ranging from 39 to 41.4 dB. During each simulation, different seeds are utilized to initialise the Gaussian number generators used to produce the white noise input and the jitter that perturbs the sampling clock.

21 Slide 21 of 26 ESA AMICSA 2006 NPR Simulation Results from a broadband space-grade ADC.  A 12 th order, Chebychev, low-pass filter with a cut-off frequency of 300 MHz is used to bandlimit the white noise input to the ADC simulation model.  An 8 th order, Butterworth, notch filter with a centre frequency of 175 MHz and a Q of 11.3 is used to provide a 15 MHz wide notch at Fs/4.

22 Slide 22 of 26 ESA AMICSA 2006 Comparison Between Simulation Results and Measured Results from Hardware Testing  The simulation environment reports an average NPR dynamic performance of 40.2 dB, ranging from 39 to 41.4 dB within the Nyquist band.  Actual NPR testing on the ADC hardware measured an average NPR (notch depth) of 40.2 dB, ranging from 38.4 to 41.3 dB within the Nyquist band.  This corresponds to a dynamic performance between 7.6 to 8.15 effective bits respectively.

23 Slide 23 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment Analogue Signal Conditioning ADC FFT Sampling Clock Generator Amplifier The simulation environment also contains behavioural models of an amplifier and an anti-aliasing filter to investigate the interaction of a more complete analog signal processing chain. The user can specify values for gain, second and third-order intercept points, the 1dB compression point, input resistance and filter cut-off frequency Anti-Aliasing LPF

24 Slide 24 of 26 ESA AMICSA 2006 Capability of Mixed-Signal Simulation Environment Analogue Signal Conditioning (1)Second-order IMP : |f2 – f1|, (2) Third-order IMP : |2f1 – f2|, (3) Fundamental f1 (4) Fundamental f2, (5) Aliased third harmonic of f2, (6) Third-order IMP : |2f2 – f1| (7)Aliased third harmonic of |2f1 + f2|, (8) Aliased third harmonic of |2f2 + f1| (9)Aliased third harmonic of f1, (10) Second harmonic of f1, (11) Second-order IMP : |f2 + f1| (12)Second harmonic of f2

25 Slide 25 of 26 ESA AMICSA 2006 Conclusion  Satellite manufacturers have access to a very limited range of ADCs/DACs that can considered for space flight – we have to ensure that we get our selection right!  A simulation environment has been developed that is being used to predict the performance of known, space-grade ADCs/DACs for many different mission types.  The simulation environment allows Astrium to carry out detailed analyses of ADC/DAC devices and predicts how the d.c. static errors affect converter and overall payload performance.  The simulation environment predicts ADC/DAC dynamic performance for typical flight-hardware conditions AND uses an input representative of a wideband, satellite comms. carrier.

26 Slide 26 of 26 ESA AMICSA 2006 Conclusion  The ADC/DAC dynamic performance information is being used to assist systems analysis allowing Astrium to predict payload performance early in the design cycle.  This is information we share with prospective customers (telecommunications operators) and our ADC/DAC semiconductor partners.


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