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1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 3: Multitasking and Memory.

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Presentation on theme: "1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 3: Multitasking and Memory."— Presentation transcript:

1 1/1/ / faculty of Electrical Engineering eindhoven university of technology Architectures of Digital Information Systems Part 3: Multitasking and Memory Management dr.ir. A.C. Verschueren Eindhoven University of Technology Section of Digital Information Systems

2 1/1/ / faculty of Electrical Engineering eindhoven university of technology Let’s build a computer... computer system CPU: 1 processor + memory my programyour program interrupt disk controller HW device driver (task) operating system (task)

3 1/1/ / faculty of Electrical Engineering eindhoven university of technology Operating system functions Maintain a task list (administration) –Know state of all tasks (ready-to-run/waiting/…) –Decide which task must run (task switching) Manage communication resources –Synchronise communicating tasks Translate interrupts into task restarts Allocate and de-allocate memory for tasks

4 1/1/ / faculty of Electrical Engineering eindhoven university of technology Playing devil (1) Unprotected systems are open to attacks ! Critical instructions can be executed –'DI' (disable interrupts) –'HALT' to crash the whole processor Hardware ports can be read and written directly –Modify or delete specific files (difficult!) –Format a random track with a single command

5 1/1/ / faculty of Electrical Engineering eindhoven university of technology Playing devil (2) Reading / writing of all memory locations possible –Modify O.S. task tables –Kill communication resources –Change another task's data or program (funny) –Fill memory with random data We assume the operating system and device drivers do not allow illegal operations!

6 1/1/ / faculty of Electrical Engineering eindhoven university of technology Protecting critical operations Give the processor hardware 'modes' to run in –'User' mode: critical operations not allowed –'System' mode: critical operations are permitted –More than two modes possible for ‘fine tuning’ Switching from system- to user mode need not be protected (we trust the operating system) Switching the other way around must be protected !

7 1/1/ / faculty of Electrical Engineering eindhoven university of technology User applications: PL 3 Intel 80286: more protection levels –Code access:only in same level or higher levels –Data access:only in same level or lower levels –Stack access:only in same level (separate stacks!) Device drivers: PL 2O.S. core: PL 1 Kernel: PL 0 PL: Privilege Level

8 1/1/ / faculty of Electrical Engineering eindhoven university of technology Switching from user to system mode (1) Generally done with a kind of software 'interrupt' –Hardware interrupt routines run in system mode too –They need the same mode switching logic but interrupts remain enabled here Interrupt routine start addresses in protected table –Not possible to enter system mode at arbitrary address –Called routine is responsible for checking parameters

9 1/1/ / faculty of Electrical Engineering eindhoven university of technology Switching from user to system mode (2) The number of ‘software interrupts’ is limited –Signetics and Zilog Z8000: ONE 'service call' Other methods exist for protected switching –DEC Alpha: protected library of subroutines –Intel 80286: pseudo segments called ’call gates’

10 1/1/ / faculty of Electrical Engineering eindhoven university of technology Protecting input/output port access Declare 'IN' and 'OUT' instructions critical –What to do with the device driver tasks? Enable and disable access on a per-port basis –Allows fine-tuning of what tasks are allowed to do Use memory mapped I/O –Let the memory protection handle the I/O protection

11 1/1/ / faculty of Electrical Engineering eindhoven university of technology Memory read/write protection Is the hardest of them all to do: There is a lot of it to protect! Must be combined with memory management Protection for different access types not enough –Read / Write / Execute (visible on bus system) Protection for different memory uses is needed –Code / Stack / Constants / Private data / Shared data

12 1/1/ / faculty of Electrical Engineering eindhoven university of technology '0' '-1' The single linear memory space model shared data A/B program B subroutine X(B) data B data X(B) stack B/X(B) program A subroutine X(A) data A data X(A) stack A/X(A) same code for subroutine X ! accessible by Aaccessible by B accessible by A and B Allowed addresses for A Allowed addresses for B Where to place the next task?

13 1/1/ / faculty of Electrical Engineering eindhoven university of technology Linear memory model disadvantages Needs a 'linking loader’ to modify programs –Programs are loaded into different memory areas each time they are run –Problems with shared subroutine libraries Inefficient use of memory Protection must be based on memory areas Programs are not protected against themselves

14 1/1/ / faculty of Electrical Engineering eindhoven university of technology '0' '-1' The multiple linear memory spaces model program A data A stack A/X(A) shared data A/B program B data B stack B/X(B) shared data A/B '0' '-1' subroutine X(B) data X(B) stack B/X(B) shared data A/B '0' '-1' subroutine X(A) data X(A) stack A/X(A) shared data A/B '0' '-1'

15 1/1/ / faculty of Electrical Engineering eindhoven university of technology Multiple linear memory spaces properties Each program can use the complete memory –More freedom in code/data placement –Higher efficiency by loading once in physical memory Protects on a 'need-to-know' basis What is invisible cannot be accessed! –Self-protection still difficult (must be address based) Requires ‘logical’ to ‘physical’ address translation

16 1/1/ / faculty of Electrical Engineering eindhoven university of technology The segmented memory model subroutine X '0'.... '0'.... data X(A) '0'.... shared data A/B '0'.... data A '0'.... program A '0'.... data X(B) '0'.... data B '0'.... program B stack A/X(A) '-1'.... stack B/X(B) '-1'.... B X(B) X(A) A

17 1/1/ / faculty of Electrical Engineering eindhoven university of technology Segmented memory properties Each memory segment in separate address space –Completely avoids the placement problem –Dynamically growing and shrinking memory segments (like stacks) are easy Protection simple: segment access rights –Address checking is a segment boundary check Segments visible on ‘need to know’ basis Needs logical to physical address translation

18 1/1/ / faculty of Electrical Engineering eindhoven university of technology Segmented memory problem Requires a major ‘philosophical’ change: ‘the address’ is split in two parts –A segment identification –An offset within the segment Automatic segment selection is partially possible –Separate segments for code and stack are obvious –Switching between different data segments requires software intervention!

19 1/1/ / faculty of Electrical Engineering eindhoven university of technology Address translation Not needed for linear memory organisation –Processor generated (logical) address  real memory (physical) address –May be handy to attach access rights to addresses Needed for multiple linear address spaces and segmented memories –Complex for multiple linear address spaces the actual address must be checked

20 1/1/ / faculty of Electrical Engineering eindhoven university of technology Table based direct address translation This table grows very large: Translating 1 million addresses with 4 access rights bits requires a 3 Megabyte table! access rights logical address physical address

21 1/1/ / faculty of Electrical Engineering eindhoven university of technology '<' compare '>=' compare Address bounds checking (1) logical address physical address physical offset access rights

22 1/1/ / faculty of Electrical Engineering eindhoven university of technology Address bounds checking (2) Parallel comparators are VERY expensive –Use a lot of power and chip area –Number of address ranges would be limited Physical address ranges must have same sizes as the logical address ranges –Memory which is organised into large (undividable) blocks is hard to manage –Same problem in a purely segmented memory

23 1/1/ / faculty of Electrical Engineering eindhoven university of technology 'page table' logical address Paging (1) bits of the address are not translated: 2 p words in a page have the same access rights access rights physical page logical page offset physical address

24 1/1/ / faculty of Electrical Engineering eindhoven university of technology Paging (2) Paging is cheaper than full address translation –Translating 1 million addresses with 1024 word pages requires a page table with only 1024 entries –With 10 bits physical page numbers and 4 access rights bits, the page table takes less than 2048 bytes! Translating 32 bit addresses with 4096 word pages requires a page table with 1 million entries! –Not all of these pages will be in use at the same time...

25 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address Second level page table First level page table Multi-level paging 2nd level table present page offset physical address Physical page access rights 2nd level table index 1st level table index

26 1/1/ / faculty of Electrical Engineering eindhoven university of technology Multi-level paging example 4 byte words, 32 bit addresses (2 bits select byte), 1024 word / 4096 byte pages ( = 10+2 bits) –Second level table: 1024 entries( = 10 bits) Entry contains 20 bit physical page number ( = 20), leaves 12 bits for access rights if each entry takes one word Each second level page table fits in one page –First level page table: 1024 entries( = 10 bits) Entry contains 20 bits physical page number of 2nd level table plus the 'table present bit' - fits easily in one word First level page table fits in one page

27 1/1/ / faculty of Electrical Engineering eindhoven university of technology Multi-level paging (continued) This address translation method is very cheap –The example second level table handles 4 MegaByte If code, data and stack fit in 8 MegaByte, we need 3 pages (12 KiloBytes) for translation Multi-level paging is not limited to 2 levels! –Motorola can go up to FIVE levels of tables Each table entry (not just the last) can specify access rights, can also give length limit for next table Searching through 5 tables for each memory access is a bit slow

28 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address '=' compare Speedup: translation lookaside buffer This 'Content Addressable Memory' lookaside buffer can reach 98% hits with ‘only’ 32 entries page offset physical address access rights 'hit!' tag

29 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address A 'set associative' lookaside buffer access rights physical page physical address 'hit!' 'tag' Cheap, simple RAM

30 1/1/ / faculty of Electrical Engineering eindhoven university of technology The problem with set associative buffers A ‘tag clash’ makes the lookaside buffer worthless –Two or more different pages used in short loop –With same bits but different (tag) bits ‘ WaitHere ’at address 35E6 h ‘ DataPort ’at address 5537 h 4 bit 8 bit 35E WaitHere:JNB DataPort.1,WaitHere Same line in table But different translation tags TWO misses per loop !

31 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address N-way set associative lookaside buffers Reduce (but do not solve) tag clashes physical page physical address Page table 1 Page table 2 mux 'hit!' hit logic 'tag' Tag table 1 Tag table 2 a.r. 1 a.r. 2 access rights mux set selection Same hit-rate as ‘Content Addressable’

32 1/1/ / faculty of Electrical Engineering eindhoven university of technology Lookaside buffer replacement strategy With filled buffer, new translations replace old –With 1-way set associative: bits fix choice! Best choice: remove one which will not be used –Difficult, but ‘Least Recently Used’ may be the same –LRU requires administration: small choice sets only –Used for N-way set associative lookaside buffers Another strategy: remove one at random –Works well with large choice sets (CAM buffers!) –Small probability of removing the wrong entry

33 1/1/ / faculty of Electrical Engineering eindhoven university of technology logical address Segmented memory address translation Segment table is in main memory ! access rights offset segment 'stack' physical address Segment bases error! ' Segment limits

34 1/1/ / faculty of Electrical Engineering eindhoven university of technology Segmented translation speedup Processor uses only a few segments at once –Place currently used segment info in on-chip registers –Software decides which segments are loaded no replacement strategy needed in hardware! Example: Intel uses 6 current segments –Code, stack and ‘default data’ –Up to 3 ‘extra data’ segments referenced explicitly

35 1/1/ / faculty of Electrical Engineering eindhoven university of technology Virtual memory (1) The logically addressable memory size can exceed the physical memory size –Common situation with multiple linear memory spaces No problem if the actually used amount of memory fits in physical memory –Rely on address translation to 'pack' the memory

36 1/1/ / faculty of Electrical Engineering eindhoven university of technology Virtual memory (2) Memory in use > physical memory: problem –Hold part of used memory in physical memory –Store remainder somewhere else, f.i. on a hard disk Keep this invisible to processor: 'virtual memory' –Hardware stops invalid memory access –Starts routine to move data into physical memory –Then re-tries the failed memory access which may be in the middle of an instruction!

37 1/1/ / faculty of Electrical Engineering eindhoven university of technology The 'program locality principle' Consecutive accesses are generally not far apart –The 'working set' contains the active memory areas –Run at full speed if these are kept in real memory! last instruction address (x) p (x+1) last stack access (y) p (y+1: POP)(y-1: PUSH) last data access (z) p (z+1: Arrays, Strings) mean stack frame size

38 1/1/ / faculty of Electrical Engineering eindhoven university of technology Virtual memory hardware support bits These work for pages as well as segments Present bit: in memory if set, otherwise on disk –Processor aborts access if this bit is reset Accessed bit: set on each read or write access –Detect activity for determining the working set Written bit: set on each write access –No need to write back to disk if unchanged

39 1/1/ / faculty of Electrical Engineering eindhoven university of technology A A A A A The ‘working set - clock’ algorithm (1) 'swap in' A acces s A A P=1 P=0 'swap out' I need you !

40 1/1/ / faculty of Electrical Engineering eindhoven university of technology The ‘working set - clock’ algorithm (2) Swap out writes only if Written bit set Swap in sets Accessed and Present, resets W This algorithm is often used (works very well) –Working set pages/segments set A bit a lot they are not swapped out! –Fair swap out decisions, even under high system load –Will always find something to swap out (robust)

41 1/1/ / faculty of Electrical Engineering eindhoven university of technology 16 K paged memory, 1 K pages ‘0’ ‘16’ The fragmentation problem 16 K segmented memory ‘0’ ‘16’ 1.5 K 2 K 2.5 K 4 K 1.5 K 4.5 K 3.5 K 1.5 K 3.5 K Unusable space inside pages !! 6 K free, but does not fit !! Memory is fragmented outside segments: external fragmentation Memory is fragmented inside pages: internal fragmentation

42 1/1/ / faculty of Electrical Engineering eindhoven university of technology Pages versus segments Fixed-size pages ease swapping to/from disk Segments provide more complete protection Intel uses segmenting AND paging –Protection based upon the segments (done first) –Virtual memory based upon paging (done last) –Two translation steps needed  The P, A and W bits are offered in hardware, managing virtual memory is done in software!

43 1/1/ / faculty of Electrical Engineering eindhoven university of technology 16 bits Intel example: ‘segment selector’ Global table with 8192 shared segments Task-local table with 8192 private segments 'Requested Privilege Level' allows lowering the protection level of a segment (towards PL 3) 'RPL’ 2 bits local/global 1 bit segment number 13 bits

44 1/1/ / faculty of Electrical Engineering eindhoven university of technology 64 bits Intel memory segment descriptor –CODEreadable, 'conforming' (for libraries) –DATAwritable, stack (reverses limit checking) –TASK STATE(registers, 4 stack pointers, active segs.) –LOCAL TABLE(only in global segment table) ‘limit’ 16 bits ‘base’ 24 bits Present 1 bit Accessed 1 bit 'PL’ 2 bits Type & access rights Location Size Virtual memory No Written bit !

45 1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel calls and jumps Within same segment only needs offset Other segment at same PL needs offset & selector To higher protected code (lower PL) uses 'call gate’ –These are stored in segment tables (‘pseudo- segment’) –CALL instruction points to this ‘pseudo-segment’ but the offset in instruction is overruled by call gate –Data copied automatically between stacks 'PL’ 2 bits Present 1 bit offset 16 bits code segment selector stack copy block size

46 1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel traps and interrupts Use 256 entry 'interrupt descriptor table’ –Which contains ‘trap gates’ and ‘interrupt gates’ –These are call gates without stack data copying –An interrupt gate disables interrupts automatically 'PL’ 2 bits Present 1 bit offset 16 bits code segment selector

47 1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel I/O protection Global 'I/O Privilege Level' indicates the highest PL value at which ANY I/O is allowed –Higher PL level code traps on IN & OUT instructions Each task has a bitmap in the task state segment –Each bit corresponds with an I/O port –Accessing I/O port with bit at 0 generates trap –Size of bitmap variable, undefined ports always trap

48 1/1/ / faculty of Electrical Engineering eindhoven university of technology Intel multitasking support 'Task state' segments store task information –Special register points to active task state segment Task switch with JUMP through a 'task gate' 'PL’ 2 bits Present 1 bit task state segment selector 1)Save register set in active task state segment 2)Get address of new task state and declare it active 3)Load register set from this segment, including PC 4)Restart program execution for the new task PL 0 only: kernel !

49 1/1/ / faculty of Electrical Engineering eindhoven university of technology '0' '-1' address space The old-fashioned way: ‘windowing’ Selection register is normally an output port –Window selection is part of memory management –Should be managed by operating system! window selection register 0 1 N - 2 N - 1 'N' windows mux ‘Expanded Memory’ 1 1 N - 1

50 1/1/ / faculty of Electrical Engineering eindhoven university of technology Built-in windowing Windowing logic can be built inside memory chips –Standard stuff for all kinds of (Flash) ROM’s –Can also save a lot of address pins! read address page register write data page register address input ROM address: Read- Only Memory 'core'

51 1/1/ / faculty of Electrical Engineering eindhoven university of technology 24 bits memory address ‘Memory mapper’ address extension –The 74LS610 provides 16 windows of 4096 bytes, each of these can select from 4096 of these windows in physical memory (total 16 million bytes!) CPU address 16 bits 4 bits 16 entries 12 bits


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