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TIMING CLOSURE IN SYSTEM-ON-CHIP ERA Sam Appleton, CEO CONFIDENTIAL.

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Presentation on theme: "TIMING CLOSURE IN SYSTEM-ON-CHIP ERA Sam Appleton, CEO CONFIDENTIAL."— Presentation transcript:

1 TIMING CLOSURE IN SYSTEM-ON-CHIP ERA Sam Appleton, CEO CONFIDENTIAL

2 Challenges in SDC Creation & Verification It can get a bit messy “IP”/block level timing Making sure design is fully constrained Finding balance between timing exceptions and risk Verification of timing environment “SoC/Chip level” timing integrating IP Ensuring Hierarchical Consistency Debugging Macro-Scale problems Size & Complexity

3 IP level timing closure It’s a balancing act! “Minimal SDC” constrain all functional paths for correctness over all modes don’t use any exceptions minimal case analysis minimal clock definitions conservative clock groups “Relaxed SDC” static path/mode exceptions added one SDC per design mode structural/formal MCPs and False Paths Clock/Data exceptions Use clocks to break up timing domains

4 The Balancing Act Low-Risk Hardest Timing, More Power & Area Higher Risk Easiest Timing, Less Power & Area 1.Find set of timing relaxations that help meet timing goals 2.Ignore all other “available” relaxations that don’t help 3.Allow for reuse of results from previous uses of IP

5 The Verification Problem “Timing domain” Verification – Debugging clocks, case, modes, conflicts – Ensure STA treatment is correct – Automating manual debug previously done with STA Functional Verification – For exceptions, functional coverage is needed – Simulation OR formal (or both) – Critical problem in signoff of timing environment

6 SoC Integration Size/Scale – M instances – clocks – IP blocks – k timing exceptions – 2 or 3 levels of hierarchy – 10000s of lines of scripting – Usually GL netlist New Level of Complexity and Scale

7 SoC Integration Challenges Leverage IP timing SDCs Make sure SoC is consistent with IPs Add toplevel constraints, make sure consistent with IPs

8 SoC/IP Consistency Critical for Hierarchical Flows Heavy use of ETMs for TAT at toplevel make this more critical Multiple causes of silicon failure Clocks Case Analysis Exceptions Boundary Budget

9 Future Directions Closing the gap between timing and functional verification – Big need to make sure the timing specification is functionally verified – SDCs are just like any other manually-created input – Finding optimal exceptions to aid in timing closure SoC integration and analysis – Bigger, more complex SoCs – Big need for hierarchical analysis and consistency tools, that can aid with promotion & demotion of SDCs


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