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Hardware ELEC 330 Digital Systems Engineering Dr. Ron Hayne.

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Presentation on theme: "Hardware ELEC 330 Digital Systems Engineering Dr. Ron Hayne."— Presentation transcript:

1 Hardware ELEC 330 Digital Systems Engineering Dr. Ron Hayne

2 330_062 Hardware Building Blocks Input/ Output Processor Control Unit Memory Clock Microcomputer/Microcontroller Microprocessor

3 330_063 Memory  Memory Signals Address Bus A 15 - A 0 Data Bus D 7 - D 0 Read/Write R/W Timing Pulse CS Tri-state outputs Mem Address Data Read/Write Timing Pulse

4 330_064 Hardware Terminology  Bus Collection of binary signal wires  68HC11 Buses 16-bit Address Bus 8-bit Data Bus Control Bus  (Non) Volatile Memory No power - no data (No power - still data)  Read/Write memory Store/retrieve at full speed  Read Only Memory Store at much slower speed  Random Access Memory Equal time for all locations  Sequential Access Read/Write in order

5 330_065 Microprocessor Bus Connections Microprocessor RAM I/O EEPROM ROM ABUSDBUS

6 330_066 Bus Operation Example  Example Instruction (STAA) Register and Memory contents  PC C100B7C100 C101C2 IR C10200  A  22  B C 

7 330_067 Instruction Fetch  PC to Memory as Address Memory contents to IR  PC C100B7C100 C101C2 IR C10200B7  A  22  B C 

8 330_068 Instruction Fetch  PC to Memory as Address Memory contents to IR  PC C100B7C101 C101C2 IR C10200B7C2  A  22  B C 

9 330_069 Instruction Fetch  PC to Memory as Address Memory contents to IR  PC C100B7C102 C101C2 IR C10200B7C200  A  22  B C 

10 330_0610 Instruction Execution  Operand Address to Memory Accumulator A contents to Memory  PC C100B7C103 C101C2 IR C10200B6C200  A  22  B C 

11 330_0611 Computer Failures  Grounded Address Bus Line Incorrect Address  Grounded Data Bus Line Incorrect Data  Intermittent Failures

12 330_0612 Memory Mapping  68HC11A8 $0000-$00FFRAM $1000-$103FI/O $B600-$B7FFEEPROM $E000-$FFFFROM 8 bits = 256 bytes 6 bits = 64 bytes 9 bits = 512 bytes 13 bits = 8K bytes RAM XXXXXXXX I/O XXXXXX EEPROM XXXXXXXXX ROM111XXXXXXXXXXXXX

13 330_0613 Creating a Memory Map  Resources 2K bytes RAM 128 bytes I/O 4K bytes EEPROM 32K bytes ROM 11 bits 7 bits 12 bits 15 bits RAM I/O EEPROM ROM

14 330_0614 Creating a Memory Map  Resources 2K bytes RAM 128 bytes I/O 4K bytes EEPROM 32K bytes ROM 11 bits 7 bits 12 bits 15 bits RAM00000XXXXXXXXXXX I/O EEPROM ROM $0000-$07FF

15 330_0615 Creating a Memory Map  Resources 2K bytes RAM 128 bytes I/O 4K bytes EEPROM 32K bytes ROM 11 bits 7 bits 12 bits 15 bits RAM00000XXXXXXXXXXX I/O EEPROM ROM1XXXXXXXXXXXXXXX $0000-$07FF $8000-$FFFF

16 330_0616 Creating a Memory Map  Resources 2K bytes RAM 128 bytes I/O 4K bytes EEPROM 32K bytes ROM 11 bits 7 bits 12 bits 15 bits RAM00000XXXXXXXXXXX I/O XXXXXXX EEPROM ROM1XXXXXXXXXXXXXXX $0000-$07FF $1000-$107F $8000-$FFFF

17 330_0617 Creating a Memory Map  Resources 2K bytes RAM 128 bytes I/O 4K bytes EEPROM 32K bytes ROM 11 bits 7 bits 12 bits 15 bits RAM00000XXXXXXXXXXX I/O XXXXXXX EEPROM0011XXXXXXXXXXXX ROM1XXXXXXXXXXXXXXX $0000-$07FF $1000-$107F $3000-$3FFF $8000-$FFFF

18 330_0618 Parallel I/O  I/O Programming Model Data Transfer Input Port  LDAA Output Port  STAA Synchronization (Timing) Flag  I/O device ready Polling  Repeatedly tests I/O flags

19 330_0619 Memory Map  THRSim11 $0000-$00FFRAM $1000-$103FI/O $B600-$B7FFRAM $E000-$FFFFROM 8 bits = 256 bytes 6 bits = 64 bytes 9 bits = 512 bytes 13 bits = 8K bytes RAM XXXXXXXX I/O XXXXXX RAM XXXXXXXXX ROM111XXXXXXXXXXXXX

20 330_0620 I/O Registers  Memory-Mapped I/O NameAddressFunction PORTA$1000Timer and Counter System PORTB$1004Parallel Output PORTC$1003Parallel Input/Output PORTCL$1005PORTC Latch PORTD$1008Serial Input/Output PORTE$100AAnalog-to-Digital Converters PIOC$1002Parallel I/O Control DDRC$1007Data Direction PORTC DDRD$1009Data Direction PORTD

21 330_0621 Parallel I/O Hardware  Output Port PORTB$1004  Input Port PORTC$1003

22 330_0622 Logical Operations  Bit Set and Clear BSET Set all bits in a memory byte that correspond to 1s in the mask BCLR Clear all bits in a memory byte that correspond to the 1s in the mask Assembly Language BSET LIGHTS,%  Bit Testing and Branching BRSET Branch if all the bits in a memory byte that correspond to 1s in the mask are set BRCLR Branch if all the bits in a memory byte that correspond to 1s in the mask are clear Assembly Language BRCLR 0,X,MASK1,NEXT

23 330_0623 Programming Example  Light PB5 if PC6 = 1 AND PC2 = 0

24 330_0624 Programming Example ** Symbol Definitions PORTC EQU $1003 PORTB EQU $1004 BIT2 EQU % BIT5 EQU % BIT6 EQU % ** Data Section ORG $10 IMAGE FCB $00 Copy of Output Bits ** Program Section Goes Here..... * Reset Vector ORG $FFFE FDB LOOP END

25 330_0625 Programming Example ** Program Section ORG $E100 * Test Input Switches LOOP LDX #PORTC BRCLR 0,X,BIT6,NEXT Test Bit-6 BRSET 0,X,BIT2,NEXT Test Bit-2 * Set IMAGE Bit-5 BSET IMAGE,BIT5 BRA OUT * Clear IMAGE Bit-5 NEXT BCLR IMAGE,BIT5 * Output to Port OUT LDAA IMAGE STAA PORTB BRA LOOP

26 330_0626 Parallel I/O Hardware  DDRC Register Data Direction Register 0input bit 1output bit  PIOC Register Parallel I/O Control Register STAF Flag Bit (7) STRA Strobe A pin PORTCL PORTC Latch Controlled by STRA pin

27 330_0627 Polling Software  Loop to Test STAF (STRA) PBTST TST PIOC BPL PBTST  Read PORTCL and Clear STAF LDAA PIOC LDAA PORTCL  Manipulate Data...

28 330_0628 Interrupt System  Main Program in Infinite Loop  When I/O Ready, Sets I/O Flag  Hardware Interrupt System Responds Stops Main Program Saves Status Transfers to Interrupt Service Routine Clears I/O Flag Transfers Data Returns Main Program Resumes Restores Status

29 330_0629 Interrupt Hardware  Interrupt Request Line (IRQ) Active Low Condition Code (I bit) Enables Interrupts Active Low CLI  I/O Flag Enable Interrupt  Stack Status (info in registers) saved Status restored on RTI  Interrupt Vectors Addresses of Interrupt Service Routines (ISR)

30 330_0630 IRQ Example  Using STAF flag to cause interrupts STAIInterrupt Enable (1 = enable) EGAEdge for STRA (1 = low-to-high) $1002STAFSTAIEGAPIOC

31 330_0631 Interrupt Program  Interrupt Vector ORG $FFF2 FDB IRQISR  Initialize Stack LDS #$B7FF  Set Up PIOC LDAA #% STAA PIOC  Enable Interrupts CLI  Wait for Interrupts HERE BRA HERE

32 330_0632 Interrupt Service Routine  Check for Valid Interrupt IRQISR LDX #PIOC BRCLR 0,X,BIT7,RTIRQ  Read Data and Clear I/O Flag LDAA PIOC LDAA PORTCL  Manipulate Data...  Return from Interrupt RTIRQ RTI

33 330_0633 Interrupt Issues  Multiple Interrupt Sources Poll flags to determine source  Interrupting an ISR Service only one interrupt at a time Queue based on priority  Concurrency Problem Different parts of program accessing common resources  Reentrancy Problem Subroutine reentered due to interrupt

34 330_0634 Summary  Memory  Buses  Memory Mapping  Parallel I/O  Interrupts


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