Presentation on theme: "1 I/O and Interrupts Today: First Hour: I/O Concepts –Section 6.1-6.6 of Huang’s Textbook –In-class Activity #1 Second Hour: Interrupt Code Example –In-class."— Presentation transcript:
1 I/O and Interrupts Today: First Hour: I/O Concepts –Section 6.1-6.6 of Huang’s Textbook –In-class Activity #1 Second Hour: Interrupt Code Example –In-class Activity #2
2 Goal: Example Task Read the output of the 4-bit data source every time the push button is pressed, and display the result. 4-bit Data Source Push Button Computer (HC11 chip) Display
3 ROM-8KB RAM-256 bytes EEPROM-512 bytes PORT A PULSE ACCUMULATOR PERIODIC INTERRUPT COP WATCHDOG PAI OC2 OC3 OC4 OC5 O C 1 IC1 IC2 IC3 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORT E V REFH V REFL A/D CONVERTER DATA DIRECTION PORT D SS SCK MOSI MISO SPI TxD RxD SCI PD5 PD4 PD3 PD2 PD1 PD0 M68HC11 CPU ADDRESS DATA BUS INTERRUPTS RESET XIRQ IRQ (V PPBULK ) 1 A 1 0 A 9 A 8 A D 7 A D 6 A D 5 A D 4 A D 3 A D 2 A D 1 A D 0 R/W AS EXPAND OSCILLATOR XTAL EXTAL E MODA LIR MODB (V STBY ) V DD V SS MODE SELECT POWER M6811 Ports
4 Ports Way to read/write from/to peripheral devices Some ports allow both input and output (see your PRG!) Each port has: –Control Registers –Status Registers –Data Registers –Data Direction Registers The ports are memory mapped, which means that you can access these registers via memory! –I/O becomes a simple matter of reading/writing to these special memory locations!
5 Look up PRG! -The 68HC11A8 has 40 I/O pins that are arranged in five I/O ports. -All I/O pins serve multiple functions. -Ports C and D are bi-directional I/O pins under the control of their associated data direction registers. -Port C, port B, the STRA pin, and the STRB pin are used for strobed and handshake parallel I/O, as well as for general-purpose I/O. Port Registers -To input, the 68HC11 reads from the port data register -To output, the 68HC11 writes into the port data register -All except port C have one data register: PORTA (at $1000) PORTB (at $1004) PORTC (at $1003) PORTCL (at $1005) PORTD (at $1008) PORTE (at $100A) 6811 Parallel I/O Using Ports
6 -Each pin of ports C and D has an associated bit in a specific data register and another in a data direction register. -The primary direction of a pin is set by its associated bit in the data direction register. - When an output pin is read, the value at the input to the pin driver is returned. -The data direction registers are cleared by reset to configure all bi-directional I/O pins for input. -Before performing I/O operation to these two ports, the software should set up the data direction registers of these two ports. Data & Direction Registers
7 Display 4-bit Data Source PORTCPORTC 0 3 4 7 0000111100001111 DDRC Data & Direction Registers
8 Which PORTC pins are Input: Output: ? Which PORTC pins are Input: Output: ? Eg: Setting I/O Pin Directions PORTC Example Program Fragment PORTCEQU$1003 DDRCEQU$1007 IO_PATEQU%11110000 NUMBEREQU%10010011... LDAA#IO_PAT STAADDRC LDAA#NUMBER STAAPORTC LDAAPORTC [3:0] [7:4] What bit pattern is output: ? What bit pattern is output: ? %1001
9 REGBASEQU$1000 PORTDEQU$08 DDRDEQU$09 LDX#REGBAS LDAA#$3F; directions of port D pins STAADDRD,X LDAA#$CD; output $CD to port D STAAPORTD,X Eg: Output to Port D
10 -All strobed mode I/O and handshake I/O are controlled by this PIOC register Parallel I/O Control Register 76543210 STAFSTAICWOMHNDSOINPLSEGAINVB value after reset 00000U11 STAF: Strobe A flag. This bit is set when a selected edge occurs on the STRA signal. STAI: Strobe A interrupt enable. When the STAF and STAI bits are both equal to 1, a hardware interrupt request will be made to the CPU. EGA: Active edge for STRA 0: falling edge 1: rising edge INVB: Invert STRB 0: STRB active low 1: STRB active high PIOC at $1002...
11 - Strobe is an external signal which can be used to trigger the I/O from the port. - Eg: Push botton ! Strobe Setup: -Strobe mode I/O selected when the bit 4 (HNDS) of the PIOC register is set to 0 and port C becomes a strobe input port. -The bit 1 (EGA) of the PIOC register when set to 1 selects the active edge of the STRA pin. - The active edge of the STRA signal latches the values of the port C pins into the PORTCL register. Strobe Input Port C
12 Strobe I/O Port C (Contd) -Reading the PORTC register returns the current values on the port C pins. -Reading the PORTCL register returns the contents of the latched PORTCL. -When enabled using bit 6 (STAI) of the PIOC, the active edge of the STRA signal will generate an interrupt to the 68HC11. -This interrupt shares the same vector as IRQ. -This can be used to force an interrupt-driven I/O !
13 Do Activity #1 Now Reference code REGBASEQU$1000 PORTDEQU$08 DDRDEQU$09 LDX#REGBAS LDAA#$3F; directions of port D pins STAADDRD,X LDAA#$CD; output $CD to port D STAAPORTD,X
14 Goal: Example Task Read the output of the 4-bit data source every time the push button is pressed, and display the result. 4-bit Data Source Push Button Computer (HC11 chip) Display
15 Recap: Polling Method 4-bit Data Source Push Button Computer (HC11 chip) Display START BUTTON PRESSED? 1 ms delay BUTTON PRESSED? READ 4-BIT INPUT UPDATE DISPLAY NO YES This style of computer input/output is called Polled I/O because we’re constantly polling the pushbutton This style of computer input/output is called Polled I/O because we’re constantly polling the pushbutton
16 Recap: Interrupt Method START INTERRUPT SERVICE ROUTINE READ THE 4-BIT INPUT UPDATE THE DISPLAY RETURN FROM INTERRUPT START INITIALIZE DO SOMETHING USEFUL Key Pressed The CPU is temporarily interrupted. An Interrupt Service Routine is entered The CPU is temporarily interrupted. An Interrupt Service Routine is entered The CPU now resumes where it left off! START INTERRUPT SERVICE ROUTINE READ THE 4-BIT INPUT UPDATE THE DISPLAY RETURN FROM INTERRUPT DO SOMETHING USEFUL
17 Interrupt Details RETURN FROM INTERRUPT (RTI) START Initialize Stack Setup Interrupt Vectors Clear previous interrupts & initialize device keeping interrupts disabled MAIN LOOP START INTERRUPT SERVICE ROUTINE Further identify source if needed Service interrupt Clear interrupt request flag* Enable interrupts locally at device Enable interrupts globally Identify source(s) Resolve priority Push registers Disable further interrupts Call interrupt service routine Restore registers Enable Interrupts Interrupt Request Done by hardware
18 Task: Hardware Setup The low nibble of PORTC is connected to a 7-segment display (output) The hi nibble of PORTC is connected to a 4-bit thumbwheel switch (input) The STRA line is connected to a high-asserting pushbutton Problem : –Copy thumbwheel setting to display whenever pushbutton is pressed. –This program should run on the EVB –Also illustrates the general form of programs using interrupts.
19 Code: initialization *Equates: define symbolic names for registers and constants PIOC EQU $1002 PORTC EQU $1003 DDRC EQU $1007 PORTCL EQU $1005 VECLOC EQU $00EE ; see EVB manual sec 3.3 the STRA line generates an IRQ interrupt JMPOP EQU $7E ; opcode for extended jmp IOPAT EQU $0F ; for data direction reg CTRPAT1 EQU %00000011 ; for PIOC reg, STAI disabled CTRPAT2 EQU %01000011 ; for PIOC reg, STAI enabled * Data Section - setup stack space and initial Stack Pointer ORG $D000 STACK RMB $7FF INITSP EQU *-1
20 Code: Init Port C * Setup and Initialization Program ORG $C000 * initialize stack pointer SETUPINT LDS #INITSP * initialize PORT C and associated control registers LDAA #CTRPAT1 ; STAI (temporarily) disabled STAA PIOC LDAA #IOPAT ; $0F => lower nibble output ; higher nibble input STAA DDRC CLR PORTC ; Clear Port C
21 Code: Setup Software IVT *setup interrupt vector in Buffalo jump table. *See section 3.3 of EVB manual for details. LDAA #JMPOP ; Load the Opcode for JMP ; at this vector location STAA VECLOC LDX #ISRIRQ ; Load the 16-bit RAM Address ; for the IRQ ISR (which is ; shared by STRA) in the next ; 2 bytes. STX VECLOC+1 ; Total:3 bytes per IVT location
22 Code: Enable Interrupts; Main *clear status of peripheral or subsystem that could cause *an immediate interrupt. See 6811 Reference manual Section 5.7, * Also see the textbook. LDAA PIOC LDAA PORTCL * Enable Interrupt in peripheral or subsystem LDAA #CTRPAT2 ; STAI enabled STAA PIOC * Enable Interrupts globally CLI; Clears I-bit in CCR. 0 => enable * Jump to main program JMP MAIN ****************************************************** * MAIN PROGRAM: trivial ****************************************************** MAIN BRA MAIN
23 Interrupt Service Routine On entry, all registers (incl. CCR with I bit) have been pushed on stack, and the I bit is set to 1 to mask further interrupts. * First check for valid interrupt. Branch to RTIIRQ if invalid. ISRIRQ LDX #PIOC BRCLR 0,X %10000000,RTIIRQ * Execute the unique recipe for clearing device interrupt flag LDAA PIOC LDAA PORTCL; Wacky !! * Service interrupt RORA RORA; Rotate 4 times RORA; Low nibble now has the 4 bits! STAA PORTC; Output to 7-segment display * Return from interrupt service routine RTIIRQ RTI ; restore registers and return to main * Note that this restores CCR (hence I bit), re-enabling interrupts. END
24 Do Activity #2 Now Due: End of Class Today. RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Huang Textbook, & HC11 PRG Required Reading: – Sec 4.1-4.7 of Huang This reading is necessary for getting points in the Studio Activity!