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Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock Synthesis Solid State Electronics Laboratory Center for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI USA International Conference on Electronic Circuits and Systems, Sharjah, U.A.E., 2003

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2 NSF ERC for Wireless Integrated MicroSystems (WIMS) Lecture Overview Overview of Clock Synthesis Effects of Frequency Translation on Frequency Stability Top-Down and Bottom-Up Synthesis Application Design and Simulation Results Conclusions and Future Work OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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3 NSF ERC for Wireless Integrated MicroSystems (WIMS) Clock Synthesis The clock is arguably the most significant signal in any synchronous system Harmonic quartz XTAL reference + PLL is the ubiquitous approach –High accuracy and stability –Broad range of output frequencies Drawbacks –Discrete components required (not monolithic) –PLL power and area –Systemic short-term stability degradation (to be presented) Challenges in developing an alternative (possibly monolithic) approach –Accuracy and stability –Monolithic reference (typically low- Q ) OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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4 NSF ERC for Wireless Integrated MicroSystems (WIMS) Short-Term Frequency Stability Metrics Phase Noise: Power relative to fundamental at some offset f m f fofo P fmfm Period Jitter: of the position of the next edge relative to the ideal Ideal Period Period Jitter tktk t k+1 OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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5 NSF ERC for Wireless Integrated MicroSystems (WIMS) Frequency Multiplication and Division Phase and frequency are related by a linear operator: Frequency mult./div. results in phase noise mult./div.: Using narrowband FM approximation: Linear freq. translation results in quadratic change in noise power Overview Freq. Trans. SynthesisApplicationDesign & Sim.ResultsConclusions

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6 NSF ERC for Wireless Integrated MicroSystems (WIMS) Converting Phase Noise to Period Jitter Typically f o 2 c called corner or line width: select f m above the corner and below f o Lorentzian implies absence of flicker noise (slope must be 20dB/dec) The SSB phase noise PSD can be represented by a Lorentzian function: fmfm 20dB/dec Which can be approximated for: Using the above: OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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7 NSF ERC for Wireless Integrated MicroSystems (WIMS) Frequency Translation and Jitter Using phase noise conversion expression, determine jitter: Considering fractional, or ppm, jitter: Frequency translation also enhances and degrades jitter OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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8 NSF ERC for Wireless Integrated MicroSystems (WIMS) Relationship with Quality-Factor Leeson model: Q -factor quadratically related to phase noise Q -factor is one of the most significant metrics indicating stability Typical quartz XTAL Q on the order of 10,000 Frequency translation also quadratically related to phase noise Consider effective Q -factor modification due to freq. translation If N div N mult > Q mult /Q div then divided signal more stable Assumption: oscillator power and noise factor are the same N mult for XTAL+ PLL up to 4096: high- Q, but large degradation Leeson Phase Noise Model OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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9 NSF ERC for Wireless Integrated MicroSystems (WIMS) Frequency Translation Summary Variable/Metric Reference Oscillator Frequency Multiplication Frequency Division Output Frequency (Hz) f ref Nf ref f ref /N SSB Phase Noise PSD (dBc/Hz) Period Jitter (s) J Relative Period Jitter (ppm) J ppm OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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10 NSF ERC for Wireless Integrated MicroSystems (WIMS) A Bottom-Up Approach ÷N Nf ref LPF v ctrl f ref CPPFD Quartz XTAL reference oscillator + PLL The signal that actually drives the processor is a frequency multiplied (and degraded) image of the reference OverviewFreq. Trans. Synthesis ApplicationDesign & Sim.ResultsConclusions

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11 NSF ERC for Wireless Integrated MicroSystems (WIMS) A Top-Down Approach ÷N f ref f ref N A harmonic LC (and monolithic) RF reference The signal that actually drives the processor is a frequency divided (and enhanced) image of the reference LC reference also provides good accuracy as compared to ring or relaxation approach OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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12 NSF ERC for Wireless Integrated MicroSystems (WIMS) Application Test Bench Intel SA-1110 –3.6864MHz XTAL reference + PLL –~200MHz max output frequency Bottom-up Approach –3.125MHz XTAL, Q = 10,000 –Output = 200MHz, N = 64 Top-down Approach –3.2GHz reference, Q = 10 –Output = 200MHz, N = 16 All transistor design with TSMC 0.18 MM/RF OverviewFreq. Trans.Synthesis Application Design & Sim.ResultsConclusions

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13 NSF ERC for Wireless Integrated MicroSystems (WIMS) Pierce Bottom-Up XTAL Reference OSC m4.79f p 7p 500k 3.125MHz XTAL reference Requires off-chip XTAL + 2 capacitors + 1 resistor XTAL lumped parameter model OverviewFreq. Trans.SynthesisApplication Design & Sim. ResultsConclusions

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14 NSF ERC for Wireless Integrated MicroSystems (WIMS) Ring Bottom-Up VCO bias from last stage 20-stage 200MHz current-starved ring VCO OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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15 NSF ERC for Wireless Integrated MicroSystems (WIMS) A Bottom-Up System LPFPFD ÷N f ref Nf ref v ctrl CP Remainder of PLL modeled with Verilog-A OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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16 NSF ERC for Wireless Integrated MicroSystems (WIMS) LC Top-Down Reference OSC nH bias 950fF 3.2GHz monolithic RF LC reference oscillator OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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17 NSF ERC for Wireless Integrated MicroSystems (WIMS) Top-Down System Implementation Entire system designed at the device level Each feedback flip-flop divides frequency by two OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions DFF Q Q D AMP GHz Q Q D Q Q D DFF Q D Q 200MHz

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18 NSF ERC for Wireless Integrated MicroSystems (WIMS) Design and Simulation Bottom-up Approach –Phase noise for reference OSC and VCO simulated at device level –Device-level results modeled with Verilog-A –Entire PLL modeled with phase domain approach using Verilog-A Top-down Approach –Entire system simulated at the device level OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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19 NSF ERC for Wireless Integrated MicroSystems (WIMS) Bottom-Up Phase Noise Performance OverviewFreq. Trans.SynthesisApplicationDesign & Sim. Results Conclusions

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20 NSF ERC for Wireless Integrated MicroSystems (WIMS) Bounding PLL Phase Noise OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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21 NSF ERC for Wireless Integrated MicroSystems (WIMS) Top-Down Phase Noise Performance OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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22 NSF ERC for Wireless Integrated MicroSystems (WIMS) Performance Comparison Performance MetricBottom-Up SynthesisTop-Down Synthesis Application Frequency, f o (MHz) 200 Reference Oscillator Frequency, f ref (MHz) ,200 Multiplication/Division Factor, N 6416 Reference Oscillator Quality Factor, Q 10,00010 Reference Oscillator Phase Noise Density, ( N o / P o ) f m (dBc/Hz) 10kHz Calculated Period Jitter at Reference from ( N o / P o ) f 10kHz offset, J (fs) Calculated Relative Period Jitter at Reference, J ppm (ppm) Synthesizer Output Phase Noise Density, ( N o / P o ) f m (dBc/Hz) 10kHz Calculated Period Jitter at Output from ( N o / P o ) f 10kHz offset, J (fs) 2923 Calculated Relative Period Jitter at Output J ppm (ppm) Phase Noise Density Accumulation/Reduction Factor, (dB) Period Jitter Accumulation/Reduction Factor Relative Period Jitter Accumulation/Reduction Factor OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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23 NSF ERC for Wireless Integrated MicroSystems (WIMS) Conclusions and Future Work Frequency multiplication degrades short term stability and effectively reduces reference oscillator Q Frequency division enhances short-term stability and effectively increases reference oscillator Q Bottom-up approach requires reference XTAL OSC + PLL while top- down approach requires only reference OSC + divider For a common application, top-down approach provides comparable frequency stability to bottom-up approach, while being substantially simpler to implement Top-down approach facilitates monolithic integration Such a clock synthesis system has been developed and will be reported in the near future More sophisticated top-down architectures will be explored OverviewFreq. Trans.SynthesisApplicationDesign & Sim.Results Conclusions

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24 NSF ERC for Wireless Integrated MicroSystems (WIMS) Conclusions and Future Work Questions? OverviewFreq. Trans.SynthesisApplicationDesign & Sim.ResultsConclusions

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