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MICROSYSTEMS LABORATORY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Microelectronic Hysteresis Robert W. Newcomb Talk for FICAMC: Plovdiv August, 16,

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Presentation on theme: "MICROSYSTEMS LABORATORY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Microelectronic Hysteresis Robert W. Newcomb Talk for FICAMC: Plovdiv August, 16,"— Presentation transcript:

1 MICROSYSTEMS LABORATORY DEPARTMENT OF ELECTRICAL & COMPUTER ENGINEERING Microelectronic Hysteresis Robert W. Newcomb Talk for FICAMC: Plovdiv August, 16, 2008 (Fifth International Conference of Applied Mathematics and Computing – Bulgaria’2008)

2 The Old Town of Plovdiv by Ivan Theofilov Your ancient floors float among the stars. Blue donkeys graze the silence around. The Roman road leads down along matrimonial chandeliers. A cry out of woman's flesh calls in the clock. Violet-colored philistines go to bed in the deep houses, they hear the pig, the hens, the train, the mouse. The darkness dawns with quick sensual pupils. The bridal veil flies away with the chimney's breath. Blue donkeys run on the moonlit roofs. Saints take off in a cloud from whitewashed churches, with blood-soaked lambs they welcome the bridal veil. Leopards gaze with amber eyes from the doorsteps. Among box trees bacchantes with satin bands pour fragrant myrrh out of bronze rhytons... Ivan Theofilov was born in Plovdiv in 1931 and graduated from the Theatre Academy in Sofia. He is an honorary citizen of Plovdiv. The poem translated here is from Geometry of the Spirit, published by Free Poetic Society, Sofia, 1996, and translated by Zdravka Mihaylova 2

3 Main topic of talk The mathematics for the design of VLSI CMOS circuits for hysteresis controlled by a voltage or current. Possible uses: Chaotic circuits, robust oscillators, memory, debouncing, pixel holding, emulation of chemical reactions, artificial neural networks, buildings in earth quakes Items for discussion: Microlectronic hysteresis concept The main idea, curve with movable load line Representation via semistate equations Key circuits used Some examples 3

4 The concept for microelectronics Hysteresis (ancient Greek = to lag behind) a)Static: piecewise multi/single valued [reason Spice won't run DC analysis on hysteresis] along with b) Dynamic: single valued given initial conditions Typical (static): binary bent 4

5 Binary hysteresis curves 5

6 Example of use for holding pixels in presence of noise 6

7 Main Idea Slide a load line, which depends upon the hysteresis input parameter, across a nonlinear function to give two or more intersections in one region. ==> 7

8 CMOS circuit and bent V-I hysteresis using inverters 8

9 CMOS bent hysteresis design curves 9

10 Designing all CMOS V-I hysteresis 10

11 CMOS inverter bent hysteresis 11

12 Hysteresis use in chaos generation 12

13 Multilevel hysteresis 13

14 Typical binary hysteresis circuit OTA = operational transconductance amplifier = voltage controlled current source 14

15 Variable hystereses 15

16 4 quadrant current mode hysteresis 16

17 Variable hysteresis from last circuit 17

18 Hysteresis in several dimensions 18 From UMCP dissertation of Yu Jiang

19 Circuit to realize 2D hysteresis 19

20 Dynamics via Semistate Equations Edx/dt = A(x) + Bu y = Cx u = input, y = output, x = semistate B, C, E constant matrices, E may be singular A(x) nonlinear to generate hysteresis 20

21 Op-amp circuit for hysteresis 21

22 Semistate equations for op-amp example 22

23 OTA circuit for hysteresis 23

24 OTA example semistate equations 24

25 OTA CMOS circuit 25

26 OTA curves 26

27 Sliding load line on OTA curve 27

28 Resulting OTA hysteresis, Iout vs Vin 28

29 OTA VLSI layout 29

30 Neural type cell circuit 30

31 Neural type cell hysteresis 31

32 CMOS resistor from OTA M9 V adj M1 M3M4 M2 V+ V- M5 M6 M7M8 Io(IR+) -Io(IR-) M10 M11 Floating resistor; can be positive or negative (by reversing green Leads to M1 & M2) 32

33 PSpice Simulation: Positive Floating Resistor Circuit Observations –Linear I-V region centered at V+ – V- = 0V –I R+ and I R- show good symmetry –V adj modulates I-V linearity range I R+ I R- V adj = -2.4v … -3.4v V adj = -3.4v … -2.4v V + – V - [V] V + – V - [V] I R+, I R- [  A] magnified 33

34 34 Reference: V. Petrov, M. Peifer, J. Timmer, “Structural Stability Analysis of a Cell Cycle Control Model,” Comptes rendus de l’Academie bulgare des Sciences, Tome 58, No. 1, 2005, pp. 19 – 24. Plot for σ 1 =- σ 2 =1, k o =1=k 2 =2k 1 u3=0.136 at = slopes Kinetic cells

35 Circuit to give I out =(I x +I y ) 2 /(2I w ) Subtract I x 2 /(2I w ) & I y 2 /(2I w )to get I=I x I y /I w Iterate (= cascade connections) to get cubic, etc. W. Gai, H. Chen, E. Seevinck, “Quadratic-translinear CMOS Multiplier divider circuit,” Electronic Letters, May 1997, p

36 Configuration to give cubic products 36

37 NPN differential pair Apply differential voltage Vd and tail current Io then Iout=I2-I1=Io·tanh(Vd/(2VT)), VT=thermal voltage=KT/Q I2+I1=Io => 2·I2=Io(1+tanh(Vd/2VT) 2·I1=Io(1-tanh(Vd/2VT) 37

38 Multiplier via npn differential pair Iout=(I4+I6)-(I3+I5) =Io·tanh(Vx/2VT)tanh(Vy/2VT) 38

39 Cubic via npn differential pair: Iout=Io·tanh(vx)tanh(vy)tanh(vz) 39

40 VLSI Transistors Two basic types with two complementary of each: MOSFET:NMOS & PMOS [piecewise square law] BJT: npn & pnp [exponential law] 40

41 NMOS Law For V GS ≤ V th I D =0 off For V GS >V th I D =  (V GS -V th ) 2 if V GS -V th  V DS saturation =  (2(V GS -V th )V DS -V DS 2 ) if V GS -V th 0 41

42 Useful CMOS current circuits 42

43 Setting up semistate equations Use graph theory: v b & i b = branch voltages and currents v t & i l = tree voltages and link (cotree) currents KCL: 0 t = C i b KVL: 0 l = T v b ==> v b = C T v t i b = T T i l i b =i device +i source =i d +i s ; v b =v d +v s by equivalences for devices i d =Y(v d ) 43

44 Useful equivalences 44

45 Example of setting up equations Cutset equations = KCL at nodes I and II 45

46 Device characterization 46

47 Final semistate equations 47

48 Idea of an extension In terms of binary hysteresis can set up a Preisach’s type of theory: Where h is binary hysteresis and w is a weight 48

49 Alternate CMOS OTA hysteresis 49

50 CMOS OTAVout/Vin hysteresis circuit 50

51 Vout/Vin OTA hysteresis 51

52 VLSI Layout for 1.2U AMI fabrication 52 6 main transistors 10ux10u, cap 38ux32u Vdd Gnd In Out Vr Vb


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