Presentation on theme: "RF Amplifier Analysis and Design Critical Specifications: Input impedance: Z in Load Impedance: Z L Frequency of operation (upper and lower 3 dB."— Presentation transcript:
RF Amplifier Analysis and Design Critical Specifications: Input impedance: Z in Load Impedance: Z L Frequency of operation (upper and lower 3 dB frequencies) Maximum “undistorted” Power into Z L Voltage Gain, Power Gain Efficiency (P out (max)/P DC ) Power Supply Requirements (V DC, I DC ) Remember: Design is the reverse of analysis. If you can’t analyze a thing, you cannot design a thing. An analysis problem has one correct solution. A design problem can have many solutions.
Transistor Equivalent Circuits DC Model For Bias Analysis/Design AC Model For Amplifier Analysis/Design (Common Base) Equivalent AC Model For Amplifier Analysis/Design (Common Emitter) DeviceV BE I B, I C, I E r e =1/g m NPN0.7 v> 00.026v/I E PNP-0.7 v< 0-0.026v/I E
Typical RF Amplifier DC Equivalent AC Equivalent
Book Example: Fig 1-11 DC/Bias Analysis 2 k 10 k 1 k 1.Assume is large, so I B can be neglected. Then: 2.Compute I E 3.Compute r e 4.Check Assumption 1. Current through the base bias resistors is 1 mA. The base current can be neglected if it is less than 5% of the resistor current, or.05 mA. …Since > 25, our assumption is valid 12 v VBVB
AC Analysis This is a general result that we will use over and over again! (eq 1-24) Include the transformer: Parasitic Coil Resistance Transformed Load Resistance Total AC Collector Resistance Transistor Voltage Gain
Frequency Analysis Input Impedance ( = 50) Power Gain
Saturation Margin Cutoff Margin V CC VEVE ICIC vCvC
AC Load Line ICIC iCiC v CE V CE Q Point (quiescent) Cutoff: i C ~ 0 Saturation: v CE ~ 0 Max P-P Undistorted Collector Voltage Swing For Symmetrical Clipping: If Then cutoff limits amplitude. If Then saturation limits amplitude.
Example 1-4 AC Load Line (Fig 1-11) I C = 1.3 mA iCiC v CE V CE = 10.7 v Max P-P Undistorted Collector Voltage Swing: V 0-pk = 3.5 v 5.1 mA 14.2 v Maximum Undistorted Power Output This will occur when the input voltage is 26 mv 0-pk or 18 mv RMS
Design is all about verification/validation and iteration. For this DC bias scheme, the optimum total AC collector resistance at resonance should be : …which is greater than the transformed load resistance of 7.2 k . If the 5 k resistor were eliminated, we would have Discussion Since the author neglected to do the load line analysis, he failed to detect the fact that with 40 mV rms input (56.5 mV 0-pk), the collector voltage would want to swing 7.7 V 0-pk. Since the maximum 0-pk voltage swing determined by the load line is 3.5 V the amplifier will go into cutoff and the tops of the sine waves will be clipped. This is still less than R c ’(opt), but....
... and the gains are: Now and This requires a transformer turns ratio of:... We can make R c ’ = R c ’(opt) if we can make
iCiC v CE V CE = 10.7 v Max P-P Undistorted Collector Voltage Swing: V 0-pk = 10.7 v 2.56 mA 21.7 v I C = 1.3 mA New AC Load Line Maximum Undistorted Power Output This will occur when the input voltage is 25.2 mv 0-pk or 17.3 mv RMS Limited by saturation
Performance Summary The table below summarizes the performance changes introduced by removing the 5k resistor and changing the turns ratio from 12 to 15: ParameterBeforeAfter Voltage Gain21 dB29 dB Power gain32 dB40 dB Max Undistorted Power-0.7 dBm7.1 dBm Bandwidth556 Khz176 KHz
Voltage, Current, and Power For the Transistor: For the AC Collector Load: Assume Maximum Power Output Condition: I c = I C V ce = V CE