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High-speed logic: Measurement (v.9a) 1 CENG3480_B2 Measurement Techniques Reference: Chapter 3 Measurement Techniques of High speed digital design, by Johnson and Graham
High-speed logic: Measurement (v.9a) 2 Revision: frequency domain processing and filtering §(1) Low-pass filter §(2) High-pass filter §(3) Band pass filter §(4) Tuned filter (narrow band pass filter) §See
High-speed logic: Measurement (v.9a) 3 Revision: Filtering is in Frequency domain not time domain §Filtering is in Frequency domain, don’t mix up with high/low amplitude levels Higher amplitude lower freq. Lower amplitude Higher freq. time amplitude
High-speed logic: Measurement (v.9a) 4 Examples of filters § RC RL R C L R Freq. gain 0dB Freq.
High-speed logic: Measurement (v.9a) 5 Analogies of Low-pass and High pass filters § High pass Low pass
High-speed logic: Measurement (v.9a) 6 A common example of a low pass filter: An operational amplifier: Diagram of gain bandwidth product, from 
High-speed logic: Measurement (v.9a) 7 (1) Low pass filter (Frequency low than F -3dB can pass, or has power gain more than 0.5) §(1) Low pass (e.g. op.amp) l At low freq, Gain=1=0dB l At -3dB cut off, gain = 0.5, = -3dB analog system VinVout Frequency Gain in dB = 20 log 10 (Vout/Vin) 0 -3dB F lowpass(-3dB) =1/2 RC 3dB cut off point B=Bandwidth Vc RC Ic(t) E.g.
High-speed logic: Measurement (v.9a) 8 (2) High pass filtering, (Frequency higher than F -3dB can pass, or has power gain more than 0.5) §High pass l At low freq, Gain=0= - dB l At -3dB cut off, gain =0.5, = -3dB 0 F -highpass(-3dB) = 1/2 (L/R) 3dB cut off point RL analog system VinVout Frequency Gain in dB = 20 log 10 (Vout/Vin) -3dB
High-speed logic: Measurement (v.9a) 9 (3) Band - Pass Filters (Frequency within a range can pass) 0dB 3dB gain Band width E.g. A band-pass filter by combining a low pass F low-pass(-3dB) filter, an ideal amplifier and a high pass F high-pass(-3dB) filter. Ideal amplifier RL
High-speed logic: Measurement (v.9a) 10 (4)Tuned filter: special case of a band-pass filter -- only a narrow band can pass §When the low pass F low-pass(-3dB), and the a high pass F high-pass(-3dB) filter are close. l Fc=center frequency, l F=bandwidth (narrow) 0dB 3dB gain Band width F Fc =1/[2 (LC) 1/2 ] Frequency R L C
High-speed logic: Measurement (v.9a) 11 Rise time and bandwidth of CRO probes §All scientific instruments have limitations §Limitations of oscilloscope systems l inadequate sensitivity Usually no problem because except most sensitive digital network, we are well above the minimum sensitivity (analogue system is more sensitive) l insufficient range of input voltage? No problem. Usually within range l limited bandwidth? some problems because all veridical amplifier and probe have a limited bandwidth §Two probes having different bandwidth will show different response. Using faster probe Using slower probe (6 MHz)
High-speed logic: Measurement (v.9a) 12 Oscilloscope probes §Components of oscilloscope systems l Input signal l Probe l Vertical amplifier §We assume a razor thin rising edge. Both probe and vertical amplifier degrade the rise time of the input signals.
High-speed logic: Measurement (v.9a) 13 §Combined effects: approximation l Serial delay l The frequency response of a probe, being a combination of several random filter poles near each other in frequency, is Gaussian. §Rise time is 10-90% rise time l When figuring a composite rise time, the squares of 10-90% rise times add §Manufacturer usually quotes 3-db bandwidth F 3db l approximations T = 0.338/F 3dB for each stage (obtained by simulation)
High-speed logic: Measurement (v.9a) 14 Example: Given: Bandwidth of probe and scope = 300 MHz Tr signal = 2.0ns Tr scope = 0.338/300 MHz = 1.1 ns Tr probe = 0.338/300 MHz = 1.1 ns T displayed = ( ) 1/2 = 2.5 ns For the same system, if T displayed = 2.2 ns, what is the actual rise time? T actual = ( – ) 1/2 = 1.6 ns
High-speed logic: Measurement (v.9a) 15 Self-inductance of a probe ground loop §A Primary factor degrading the performance §Current into the probe must traverse the ground loop on the way back to source §The equivalent circuit of the probe is a RC circuit §The self-inductance of the ground loop, represented on our schematic by series inductance L1, impedes these current.
High-speed logic: Measurement (v.9a) 16 §Typically, 3 inches (of 0.02” Gauge wire loop) wire on ground plane equals to (approx) 200 nH §Input C = 10pf §T LC = (LC) 1/2 = 1.4ns §T = 3.4 T LC = 4.8ns §This will slow down the response a lot.
High-speed logic: Measurement (v.9a) 17 Estimation of circuit Q §Output resistance of source combine with the loop inductance & input capacitance is a ringing circuit. §Where §Q is the ratio of energy stored in the loop to energy lost per radian during resonant decay. §Fast digital signals will exhibit overshoots. We need the right R s to damp the circuit. On the other hand, it slows down the response.
High-speed logic: Measurement (v.9a) 18 §Impact: probe having ground wires, when using to view very fast signals from low-impedance source, will display artificial ringing and overshoot. §A 3” ground wire used with a 10 pf probe induces a 2.8 ns 10-90% rise time. In addition, the response will ring when driven from a low- impedance source.
High-speed logic: Measurement (v.9a) 19 Remedy §Try to minimize the earth loop wire l Grounding the probe close to the signal source Back to page 29
High-speed logic: Measurement (v.9a) 20 Spurious signal pickup from probe ground loops §Mutual inductance between Signal loop A and Loop B where l A1 (A2) = areas of loops l r = separation of loops l Refer to figure for values. l In this example, L M = 0.17nH §Typically IC outputs l max dl/dt = 7.0 * 10 7 A/s §12mV is not a lot until you have a 32-bit bus; must try to minimize loop area
High-speed logic: Measurement (v.9a) 21 A Magnetic field detector §Make a magnetic field detector to test for noise
High-speed logic: Measurement (v.9a) 22 How probes load down a circuit §Common experience l Circuit works when probe is inserted. It fails when probe is removed. §Effect is due to loading effect, impendence of the circuit has changed. The frequency response of the circuit will change as a result. §To minimize the effect, the probe should have no more than 10% effect on the circuit under test. l E.g. the probe impedance must be 10 times higher than the source impedance of the circuit under test.
High-speed logic: Measurement (v.9a) 23 An experiment showing the probe loading effect §A 10 pf probe looks like 100 ohms to a 3 ns rising edge §Less probe capacitance means less circuit loading and better measurements. A 10 pf probe loading a 25 ohm circuit
High-speed logic: Measurement (v.9a) 24 Special probing fixtures §Typical probes with 10 pf inputs and one 3” to 6” ground wire are not good enough for anything with faster than 2ns rising edges §Three possible techniques to attack this problem l Shop built 21:1 probe l Fixtures for a low-inductance ground loop l Embedded Fixtures for probing
High-speed logic: Measurement (v.9a) 25 Shop-built 21:1 probe §Make from ordinary 50 ohm coaxial cable §Soldered to both the signal (source) and local ground §Terminates at the scope into a 50-ohm BNC connector §Total impedance = 1K + 50 ohms; if the scope is set to 50 mv/divison, the measured value is = 50 * (1050/50) = 1.05 V/division
High-speed logic: Measurement (v.9a) 26 Advantages of the 21:1 probe §High input impedance = 1050 ohm §Shunt capacitance of a 0.25 W 1K resistor is around 0.5 pf, that is small enough. l But when the frequency is really high, this shunt capacitance may create extra loading to the signal source. §Very fast rise time, the signal source is equivalent to connecting to a 1K load, the L/R rise time degradation is much smaller than connecting the signal to a standard 10 pf probe.
High-speed logic: Measurement (v.9a) 27 Fixtures for a low-inductance ground loop §Refer to figure on page 19page 19 §Tektronix manufactures a probe fixture specially designed to connect a probe tip to a circuit under test.
High-speed logic: Measurement (v.9a) 28 Embedded Fixture for Probing §Removable probes disturb a circuit under test. Why not having a permanent probe fixture? §The example is a very similar to the 21:1 probe. It has a very low parasitic capacitance of the order 1 pf, much better than the 10 pf probe. l Use the jumper to select external probe or internal terminator.
High-speed logic: Measurement (v.9a) 29 Avoiding pickup from probe shield currents §Shield is also part of a current path. §Voltage difference exists between logic ground and scope chassis; current will flow. §This “shield current * shield resistance R shield “ will produce noise V shield
High-speed logic: Measurement (v.9a) 30 §V Shield is proportional to shield resistance, not to shield inductance because the shield and the centre conductor are magnetically coupled. Inductive voltage appear on both signal and shield wires. §To observe V Shield l Connect your scope tip and ground together l Move the probe near a working circuit without touching anything. At this point you see only the magnetic pickup from your probe sense loop l Cover the end of the probe with Al foil, shorting the tip directly to the probe’s metallic ground shield. This reduces the magnetic pickup to near zero. l Now touch the shorted probe to the logic ground. You should see only the V Shield
High-speed logic: Measurement (v.9a) 31 Solving V Shield problem §Lower shield resistance (not possible with standard probes) §Add a shunt impedance between the scope and logic ground. l Not always possible because of difficulties in finding a good grounding point §Turn off unused part during observation to reduce voltage difference l Not easy §Use a big inductance (magnetic core) in series with the shield l Good for high frequency noise. l But your inductor may deteriorate at very high frequency. §Redesign board to reduced radiated field. l Use more layers §Disconnect the scope safety ground l Not safe
High-speed logic: Measurement (v.9a) 32 §Use a 1:1 probe to avoid the 10 time magnification when using 10X probe §Use a differential probe arrangement
High-speed logic: Measurement (v.9a) 33 Viewing a serial data transmission system §Jitter observed due to intersymbol interference and additive noise. §To study signal, probe point D and use this as trigger as well.
High-speed logic: Measurement (v.9a) 34 §No jitter at trigger point due to repeated syn with positive- going edge. l This could be misleading §For proper measurement, trigger with the source clock l The jitter is around half of the previous one. l If source clock is not available, trigger on the source data signal point A or B (where is minimal jitter)
High-speed logic: Measurement (v.9a) 35 Slowing Down the System clock §Not easy to observe high speed digital signals which include ringing, crosstalk and other noises. §Trigger on a slower clock (divide the system clock) allows better observations because it allows all signals to decay before starting the next cycle. §It will help debugging timing problems.
High-speed logic: Measurement (v.9a) 36 Observing crosstalk §Crosstalk will l Reduce logic margins due to ringing l Affect marginal compliance with setup and hold requirements l Reduce the number of lines that can be packed together §Use a 21:1 probe to check crosstalk l Connect probe and turn off machine; measure and make sure there is minimal environment noise. l Select external trigger using the suspected noise source l Then turn on machine to observe the signal which is a combination of primary signal, ringing due to primary signal, crosstalk and the noise present in our measurement system
High-speed logic: Measurement (v.9a) 37
High-speed logic: Measurement (v.9a) 38 §Try one of the followings to observe the cross talk l Turn off primary signal (or short the bus drivers) Varying the possible noise source signal (e.g. signal patterns for the bus) l Compare signals when noise source is on and off Talk photos with the suspected noise source ON and source OFF. The difference is the crosstalk l Generating artificial crosstalk Turn off, disabled, short the driving end of the primary signal. Induce a step edge of know rise time on the interfering trace and measure the induced voltage. Useful technique when measuring empty board without components.
High-speed logic: Measurement (v.9a) 39 Measuring Operating Margins §In digital system measurements, we are interested to stress the system to ensure the system is within operation margin specified. §Make sure the arrangement is automatic and self recovery §Some of the common tests l Additive noise Add random noise to every node Sine waves, square waves or random pattern Difficult to administer Suitable for data receivers and transmitters l Adjusting the timing of a large bus (clock skew margin test) Test the combine effects of system setup time, hold time and operating margin etc. Connect the devices’ clock signals using the following methods. –Clock adjustment by coax delay (vary the length) –Clock adjustment by pulse generator (variable delays) –Simple circuits for clock phase adjustment –Clock adjustment by a phase-locked loop –Clock adjustment by voltage variation
High-speed logic: Measurement (v.9a) 40 l Power Supply Power supply variation can change response characteristics Vary the supply over a + 10% range l Temperature Temperature will vary the delay characteristics Can use cooling spray, blow dryer etc. Some companies use temperature control ovens Make sure the temperature probe is attached to the right place l Data Throughput Compose a suite of operations that exercise each individual connections Not easy to compose test pattern that represents the real situations. Often system passes tests but fails at real operations. Good data pattern will uncover unexpected avenues of noise coupling which causes failures Complex tests are expensive