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CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic C: State Assignment José Nelson Amaral.

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Presentation on theme: "CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic C: State Assignment José Nelson Amaral."— Presentation transcript:

1 CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 Topic C: State Assignment José Nelson Amaral

2 CMPUT Computer Organization and Architecture II2 Reading Assignment Chapter 7, section 7.4.6

3 CMPUT Computer Organization and Architecture II3 Incompletely Specified State Tables Network ANetwork C Sequential Network B X Z Assumptions: (i) Network A can only generate sequences X=100 and X = 110. (ii) Network B produces output Z=1 when it receives X=110 and output Z=0 for X=100 (iii) Network C ignores values of Z at other times.

4 CMPUT Computer Organization and Architecture II4 Incompletely Specified State Tables S0 1/- S1

5 CMPUT Computer Organization and Architecture II5 Incompletely Specified State Tables S0 S1 1/- S3 S2 0/- 1/-

6 CMPUT Computer Organization and Architecture II6 Incompletely Specified State Tables S0 S1 1/- S3 S2 0/- 1/- 0/0

7 CMPUT Computer Organization and Architecture II7 Incompletely Specified State Tables S0 S1 1/- S3 S2 0/- 1/- 0/0 0/1 Whenever there is a don’t care state or a don’t care output, I can fill it with any value.

8 CMPUT Computer Organization and Architecture II8 Incompletely Specified State Tables Therefore, I should fill it in a way that allows minimization of the state machine. S0 S1 1/- S3 S2 0/- 1/- 0/0 0/1

9 CMPUT Computer Organization and Architecture II9 Incompletely Specified State Tables Therefore, I should fill it in a way the allows minimization of the state machined. S0 S1 1/- S3 S2 0/- 1/- 0/1 0/- S0 0/0

10 CMPUT Computer Organization and Architecture II10 Incompletely Specified State Tables Therefore, I should fill it in a way the allows minimization of the state machined. S0 S1 1/- S3 S2 0/- 1/- 0/1 0/- S0 0/0

11 CMPUT Computer Organization and Architecture II11 Incompletely Specified State Tables Therefore, I should fill it in a way the allows minimization of the state machined. S0 S1 1/- S3 S2 0/- 1/- 0/1 S0 0/0 S1 1/-

12 CMPUT Computer Organization and Architecture II12 Incompletely Specified State Tables S0 S1 1/- 0/1 0/0 1/-

13 CMPUT Computer Organization and Architecture II13 Do State Assignments Matter? S0S0 S4S4 S3S3 S2S2 S1S

14 CMPUT Computer Organization and Architecture II14 State and Output Equations for Asgn #1 Q1Q1 D 2 = Q 1 ’ I 0 ’ + Q 2 ’ I 0 ’ + Q 1 Q 0 ’ Q0Q0 1 1 XX 1 1 XX XX1 Q2Q2 I0I0

15 CMPUT Computer Organization and Architecture II15 State and Output Equations for Asgn #1 Q0Q0 1 XX XX 1 XX1 Q1Q1 Q2Q2 I0I0 D 2 = Q 1 ’ I 0 ’ + Q 2 ’ I 0 ’ + Q 1 Q 0 ’ D 1 = Q 1 Q 2 ’ + Q 2 Q 1 ’ + Q 2 ’ I 0

16 CMPUT Computer Organization and Architecture II16 State and Output Equations for Asgn #1 Q0Q0 1 XX XX XX1 Q1Q1 Q2Q2 I0I0 D 2 = Q 1 ’ I 0 ’ + Q 2 ’ I 0 ’ + Q 1 Q 0 ’ D 1 = Q 1 Q 2 ’ + Q 2 Q 1 ’ + Q 2 ’ I 0 D 0 = Q 2 Q 1 ’I 0 ’ + Q 2 ’Q 0 ’ I 0 + Q 1 Q 2 ’I 0 ’

17 CMPUT Computer Organization and Architecture II17 State and Output Equations for Asgn #1 Q0Q0 1 XX XX XX1 Q1Q1 Q2Q2 I0I0 D 2 = Q 1 ’ I 0 ’ + Q 2 ’ I 0 ’ + Q 1 Q 0 ’ D 1 = Q 1 Q 2 ’ + Q 2 Q 1 ’ + Q 2 ’ I 0 D 0 = Q 2 Q 1 ’I 0 ’ + Q 2 ’Q 0 ’ I 0 + Q 1 Q 2 ’I 0 ’

18 CMPUT Computer Organization and Architecture II18 State and Output Equations for Asgn #1 Q0Q0 1 XX 1 X Q1Q1 Q2Q2 D 2 = Q 1 ’ I 0 ’ + Q 2 ’ I 0 ’ + Q 1 Q 0 ’ D 1 = Q 1 Q 2 ’ + Q 2 Q 1 ’ + Q 2 ’ I 0 D 0 = Q 2 Q 1 ’I 0 ’ + Q 2 ’Q 0 ’ I 0 + Q 1 Q 2 ’I 0 ’ Z 0 = Q 2 ’Q 0 + Q 2 Q 1 ’

19 CMPUT Computer Organization and Architecture II19 State and Output Equations for Asgn #1 Q0Q0 1 XX 1X Q1Q1 Q2Q2 D 2 = Q 1 ’ I 0 ’ + Q 2 ’ I 0 ’ + Q 1 Q 0 ’ D 1 = Q 1 Q 2 ’ + Q 2 Q 1 ’ + Q 2 ’ I 0 D 0 = Q 2 Q 1 ’I 0 ’ + Q 2 ’Q 0 ’ I 0 + Q 1 Q 2 ’I 0 ’ Z 0 = Q 2 ’Q 0 + Q 2 Q 1 ’ Z 1 = Q 1 Q 0 ’ + Q 2 Q 1 ’

20 CMPUT Computer Organization and Architecture II20 State and Output Equations for Asgn #1 same term, only pay for it once

21 CMPUT Computer Organization and Architecture II21 State and Output Equations for Asgn #2 Q0Q0 Q2Q2 I0I0 Q1Q1 D 2 = XXXX XX 1 1 D 2 = Q 2 ’Q 1 ’

22 CMPUT Computer Organization and Architecture II22 State and Output Equations for Asgn #2 Q0Q0 XXXX XX Q2Q2 I0I0 Q1Q1 D 2 = Q 2 ’Q 1 ’ D 1 =D 1 = Q D 1 = Q 2 + Q 0 D 1 = Q 2 + Q 0 + Q 1 ’I 0

23 CMPUT Computer Organization and Architecture II23 State and Output Equations for Asgn #2 Q0Q0 XXXX XX Q2Q2 I0I0 Q1Q1 D 0 = D 2 = Q 2 ’Q 1 ’ D 1 = Q 2 + Q 0 + Q 1 ’I 0 D 0 = Q 2 I 0 1 1

24 CMPUT Computer Organization and Architecture II24 State and Output Equations for Asgn #2 Q0Q0 XX X Q1Q1 Q2Q2 Z 0 = D 0 = Q 2 I 0 D 2 = Q 2 ’Q 1 ’ D 1 = Q 2 + Q 0 + Q 1 ’I Z 0 = Q 2

25 CMPUT Computer Organization and Architecture II25 State and Output Equations for Asgn #2 Q0Q0 XX X Q1Q1 Q2Q2 Z 1 = Z 0 = Q 2 D 0 = Q 2 I 0 D 2 = Q 2 ’Q 1 ’ D 1 = Q 2 + Q 0 + Q 1 ’I 0 Z 1 = Q 0 Z 1 = Q 0 + Q 2 Q 1 ’ 1 1

26 CMPUT Computer Organization and Architecture II26 State and Output Equations for Asgn #2

27 CMPUT Computer Organization and Architecture II27 State and Output Equations for Asgn #

28 CMPUT Computer Organization and Architecture II28 How to choose a state assignment? What makes one assignment yield a set of equations with a cost of 36 and another assignment result in a set of equations with a cost of 13? How can we choose the best state assignment for a given state machine? Could we try all assignments by enumeration?

29 CMPUT Computer Organization and Architecture II29 Number of State Assignments Given a finite state machine M with r states. Assume that we use s bits to encode the states, where s is the smallest integer such that 2 s  r. How many state assigments can be made to this machine?

30 CMPUT Computer Organization and Architecture II30 Number of State Assignments How many state assigments can be made to this machine?

31 CMPUT Computer Organization and Architecture II31 Number of State Assignments How many state assigments can be made to this machine?

32 CMPUT Computer Organization and Architecture II32 Number of State Assignments How many state assigments can be made to this machine?

33 CMPUT Computer Organization and Architecture II33 Equivalent State Assignments (Definition 1) How many of these state assigments are equivalent to each other? State Equivalency (McCluskey and Unger, 1959): State assignments are equivalent if they differ only by the re-ordenation of the columns of bits in each assignment, or if they differ by complementing a columns of the matrix.

34 CMPUT Computer Organization and Architecture II34 Equivalent State Assignments (Definition 2) But, in 1967 Weiner and Smith showed that assignments that result from complementing a column of bits are not equivalent to each other. Therefore their definition of state equivalency is: State Equivalency (Weiner and Smith, 1967): State assignments are equivalent if they differ only by the re-ordenation of columns.

35 CMPUT Computer Organization and Architecture II35 Equivalent State Assignments (Example) Which of the following state assignments are equivalent? (a) (b) (c) (d)

36 CMPUT Computer Organization and Architecture II36 Number of Distinct State Assignments Given a finite state machine M with r states. Assume that we use s bits to encode the states, where s is the smallest integer such that 2 s  r. How many distinct assignments exist for this machine?

37 CMPUT Computer Organization and Architecture II37 Number of Distinct State Assignments By McCluskey’s definition (1959), the number of equivalent state assignments is given by: Using Weiner-Smith’s definition (1967), Harrison found (in 1968) that the number of equivalent state assignments is:

38 CMPUT Computer Organization and Architecture II38 Number of Distinct State Assignments A: State Assignments N1: Distinct State Assign. (McCluskey) N2: Distinct State Assign. (Weiner-Smith-Harrison)

39 CMPUT Computer Organization and Architecture II39 Number of Distinct States Assignments A: State Assignments N1: Distinct State Assignments (McCluskey) N2: Distinct State Assign. (Weiner-Smith-Harrison)

40 CMPUT Computer Organization and Architecture II40 The Right Number of Distinct States In 1977, Rhyne and Noe showed that: (I) for circuits built with flip-flops SR, JK, and T, there are N1 (McCluskey) distinct states. (ii) for machines implemented with flip-flops D, there are N2 (Weiner-Smith-Harrison) distinct states.

41 CMPUT Computer Organization and Architecture II41 Finding an Optimal State Assignment It seems that we will not be able to enumerate all possible state assignments, generate the next state and output equations, compute the cost and then choose the best one. As a matter of fact, the State Assignment Problem (SAP) is a well-known NP-complete problem. Therefore we must settle for “good” state assignments.

42 CMPUT Computer Organization and Architecture II42 Distance Between States The distance between two states S a and S b, D(S a,S b ) is defined as the Hamming distance between the code assigned to S a, A(S a ), and the code assinged to S b, A(S b ).

43 CMPUT Computer Organization and Architecture II43 Distance Between States (Example) As an example lets compute the distance to state S 0 of every other state in our example

44 CMPUT Computer Organization and Architecture II44 Distance Between States (Example) As an example lets compute the distance to state S 0 of every other state in our example

45 CMPUT Computer Organization and Architecture II45 State Distance Graph State Distance Graph(Asgn #1) State Distance Graph(Asgn #2)

46 CMPUT Computer Organization and Architecture II46 The Successor Rule Good state assignments result when the following set of empirical rules are followed in the selection of the state assignment: Rule 1: States that are the next states of a given state should be close to each other SiSi SjSj SkSk 0 1 Suc(S i ) = {S j, S k } S j and S k should be close to each other

47 CMPUT Computer Organization and Architecture II47 The Successor Rule (Example) State Distance Graph(Asgn #1) State Distance Graph(Asgn #2) Assign #2 better satisfies the successor rule than Assign #1

48 CMPUT Computer Organization and Architecture II48 The Predecessor Rule Rule 2: States that have the same next state, for a given input, should be close to each other. ScSc SaSa SbSb I 0 =1 Pred(S c, I 0 =1) = {S a, S b } S a and S b should be close to each other I 0 =1

49 CMPUT Computer Organization and Architecture II49 The Predecessor Rule (Example) State Distance Graph(Asgn #1) State Distance Graph(Asgn #2) Assign #2 better follows the predecessor rule than Assign #1

50 CMPUT Computer Organization and Architecture II50 The Output Rule Rule 3: States that have the same output for a given input should be close to each other. For a Moore machine we say that each output partitions the states into two subsets.

51 CMPUT Computer Organization and Architecture II51 The Output Rule (Example) For a Moore machine we say that each output partitions the states into two subsets. In our example: O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )}

52 CMPUT Computer Organization and Architecture II52 The Output Rule (Example) State Distance Graph(Asgn #1) State Distance Graph(Asgn #2) O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )} Assign #2 better follows the output rule for Z 0

53 CMPUT Computer Organization and Architecture II53 The Output Rule (Example) State Distance Graph(Asgn #1) State Distance Graph(Asgn #2) O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )} Assign #2 better follows the output rule for Z 1

54 CMPUT Computer Organization and Architecture II54 The Transition Rule Rule 4: If there is a state transition between two states, the states should be close to each other. Typically this rule is used to decide a tie between the other rules.

55 CMPUT Computer Organization and Architecture II55 The Transition Rule (Example) State Distance Graph(Asgn #1) State Distance Graph(Asgn #2) Assign #2 better follows the transition rule

56 CMPUT Computer Organization and Architecture II56 The State “0” Guideline Guideline: The cost of the circuit will not be affected by the choice of which state receives the state “0” (according to McCluskey). Therefore to simplify reset generating circuits, the state “0” should always be assigned to the reset state.

57 CMPUT Computer Organization and Architecture II57 Successor Sets Using our definitions, we can compute the set of successors of each state in our example: S(S 0 ) = {S 1, S 2 } S(S 1 ) = {S 3, S 4 } S(S 2 ) = {S 3, S 4 } S(S 3 ) = {S 4 } S(S 4 ) = {S 0 }

58 CMPUT Computer Organization and Architecture II58 Predecessor Sets We can also compute the set of predecessors of each state in our example: P (S 1,I 0 =0) = {S 0 } P (S 4,I 0 =0) = {S 1, S 2, S 3 } P (S 0,I 0 =0) = {S 4 } P (S 2,I 0 =1) = {S 0 } P (S 3,I 0 =1) = {S 1, S 2 } P (S 4,I 0 =1) = {S 3 } P (S 0,I 0 =1) = {S 0 }

59 CMPUT Computer Organization and Architecture II59 Sets and Output Partition (Example) Thus for our example we have: Predecessor Sets: P (S 1,I 0 =0) = {S 0 } P (S 4,I 0 =0) = {S 1, S 2, S 3 } P (S 0,I 0 =0) = {S 4 } P (S 2,I 0 =1) = {S 0 } P (S 3,I 0 =1) = {S 1, S 2 } P (S 4,I 0 =1) = {S 3 } P (S 0,I 0 =1) = {S 0 } Output Partitions: O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )} Successor Sets: S(S 0 ) = {S 1, S 2 } S(S 1 ) = {S 3, S 4 } S(S 2 ) = {S 3, S 4 } S(S 3 ) = {S 4 } S(S 4 ) = {S 0 } But we are only interested in sets with multiple elements.

60 CMPUT Computer Organization and Architecture II60 Sets and Output Partition (Example) Thus for our example we have: Predecessor Sets: P (S 4,I 0 =0) = {S 1, S 2, S 3 } P (S 3,I 0 =1) = {S 1, S 2 } Output Partitions: O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )} Successor Sets: S(S 0 ) = {S 1, S 2 } S(S 1 ) = {S 3, S 4 } S(S 2 ) = {S 3, S 4 }

61 CMPUT Computer Organization and Architecture II61 Obtaining Good State Assignments (Example) Predecessor Sets: P (S 4,I 0 =0) = {S 1, S 2, S 3 } P (S 3,I 0 =1) = {S 1, S 2 } Output Partitions: O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )} Successor Sets: S(S 0 ) = {S 1, S 2 } S(S 1 ) = {S 3, S 4 } S(S 2 ) = {S 3, S 4 } Problem: Choose a good state assignment for this machine.

62 CMPUT Computer Organization and Architecture II62 The Desired Adjacency Graph (DAG) Based on early work of Armstrong (1962), Amaral (1990) incorporated the state assignment rules of Miller (1965) into a “Desired Adjacency Graph” that can be used to translate the state assignment rules into a graph that encodes the strenght of the connection between states. J. N. Amaral and W. C. Cunha, “State Assignment Algorithm for Incompletely Specified Finite State Machines,” in Fifth Congress of the Brazilian Society for Microelectronics, pp , J. N. Amaral, K. Tumer, and J. Ghosh, “Designing Genetic Algorithms for the State Assignment Problem,” IEEE Transactions on Systems, Man, and Cybernetics, vol. 25, No. 4, April, 1995.

63 CMPUT Computer Organization and Architecture II63 The Successor DAG Successor Sets: S(S 0 ) = {S 1, S 2 } S(S 1 ) = {S 3, S 4 } S(S 2 ) = {S 3, S 4 } To create the successor DAG, we start with a graph with zero associated to all edges and add 1 to the edge (S a, S b ) whenever S a and S b are elements of the successor set of a state. Successor Desired Adjacency Graph

64 CMPUT Computer Organization and Architecture II64 The Predecessor DAG Predecessor Desired Adjacency Graph Predecessor Sets: P (S 4,I 0 =0) = {S 1, S 2, S 3 } P (S 3,I 0 =1) = {S 1, S 2 } To create the predecessor DAG, we start with a graph with zero associated to all edges and add 1 to the edge (S a, S b ) whenever S a and S b are elements of the predecessor set of a state.

65 CMPUT Computer Organization and Architecture II65 The Output DAG Output Desired Adjacency Graph Output Partitions: O(Z 0 ) = {(S 0, S 3, S 4 ), (S 1, S 2 )} O(Z 1 ) = {(S 0, S 2, S 4 ), (S 1, S 3 )} To create the output DAG, we start with a graph with zero associated to all edges and add 1 to the edge (S a, S b ) whenever S a and S b are in the same partition for an output Z p.

66 CMPUT Computer Organization and Architecture II66 The Transition DAG Transition Desired Adjacency Graph To create the transition DAG, we start with a graph with zero associated to all edges and add 1 to the edge (S a, S b ) whenever there is a transition from state S a to state S b.

67 CMPUT Computer Organization and Architecture II67 Combining DAGS Output DAGPredecessor DAGSuccessor DAG How do we combine these four DAGs to obtain a single one? Transition DAG

68 CMPUT Computer Organization and Architecture II68 The Weight of the Rules If all the rules were equally important, we could just add the values in the vertices. Comer [1984] suggests that Rule 2 (the predecessor rule) is the most important, followed by Rule 1 (the successor rule), and by Rule 3 (the output rule). Rule 4 (the transition rule) should be used only as a tie breaker. Amaral [1990] proposes the following weights for the combination of the Rule DAGs into a single DAG: DAG = 3xSuccessor + 4xPredecessor + 2xOutput + Transition

69 CMPUT Computer Organization and Architecture II69 Output DAGPredecessor DAGSuccessor DAG Transition DAG DAG = 3xSuccessor + 4xPredecessor + 2xOutput + Transition DAG

70 CMPUT Computer Organization and Architecture II70 How Asgn #2 and Asgn #2 measure up? DAG State Distance Graph(Asgn #1) State Distance Graph(Asgn #2)

71 CMPUT Computer Organization and Architecture II71 Matching Code Distances with the DAG DAG Code Distances

72 CMPUT Computer Organization and Architecture II72 Where to Start the State Assignment? DAG First we compute the Weight of each state S a by adding the values associated with the edges (S a, S ? ) in the DAG. This weight vector indicates which states should be given priority during the state assignment process. Weight

73 CMPUT Computer Organization and Architecture II73 Matching Code Distances with the DAG

74 CMPUT Computer Organization and Architecture II74 The Weight of the States DAG Weight We start with the state with the largest weight.

75 CMPUT Computer Organization and Architecture II75 The First State Assignment DAG Weight We start with the state with the largest weight. If there is a tie, we start with the state (among the ones that tie) that has an edge with maximum value in the DAG. We assign “0” to this state.

76 CMPUT Computer Organization and Architecture II76 The Second State Assignment DAG Weight We start with the state with the largest weight. If there is a tie, we start with the state (among the ones that tie) that has an edge with maximum value in the DAG. We assign “0” to this state. Then find the state with the strongest connection with that first state in the DAG and assign “1” to this second state.

77 CMPUT Computer Organization and Architecture II77 Incomplete Assignment Table DAG Each cell of the table contains how much would be added to the expression If the state of the row would be given the code of the column

78 CMPUT Computer Organization and Architecture II78 Incomplete Assignment Table DAG Thus the value at cell (S0,010) is:

79 CMPUT Computer Organization and Architecture II79 Incomplete Assignment Table DAG The value in the other cells is computed in the same way

80 CMPUT Computer Organization and Architecture II80 Incomplete Assignment Table DAG Then we add the values in each row.

81 CMPUT Computer Organization and Architecture II81 Selecting a State in the IAT DAG The state that has the heighest sum in the table is the one that can cause the most damage (increase the cost of the circuit). Therefore it should be assigned first.

82 CMPUT Computer Organization and Architecture II82 Selecting States in the IAT DAG Thus we look for the row with maximum sum in the Incomplete Assignment Table, and we pick the cell with the minimum weight. If there is a tie, we break it arbitrarily.

83 CMPUT Computer Organization and Architecture II83 Incomplete Assignment Table DAG Now we have to recompute the values in the table. Again we pick the minimum cell in the row with the maximum sum.

84 CMPUT Computer Organization and Architecture II84 Incomplete Assignment Table DAG Again we recompute the values in the table. We pick the minimum cell in the row.

85 CMPUT Computer Organization and Architecture II85 Checking the State Distance Graph DAG Does this assignment make sense? To make checking it easier, we can build a state distance graph. State Distance Graph

86 CMPUT Computer Organization and Architecture II86 Incomplete Assignment Table But this assignment does not follow the guideline that says that the reset state (S 0 ) should be state “0”. To fix that, we have to complement the two first columns. Would that change the state distance graph?

87 CMPUT Computer Organization and Architecture II87 Incomplete Assignment Table DAG Assign #3 State Distance Graph

88 CMPUT Computer Organization and Architecture II88 Comparing Assignments #1, #2, and #3 DAG Assign #1 Assign #2 Assign #3

89 CMPUT Computer Organization and Architecture II89 State and Output Equations for Asgn #3

90 CMPUT Computer Organization and Architecture II90 D 2 Equations for Asgn #3 Q0Q0 1 X XX X1 XX Q2Q2 I0I0 Q1Q1 D 2 = Q 1 ’ Asgn #3

91 CMPUT Computer Organization and Architecture II91 Comparing D 2 Equation for Asgn #3 and Asgn #1 Q0Q0 1 X XX X1 XX Q2Q2 I0I0 Q1Q1 Q0Q0 1 XX 1 XX XX Q2Q2 I0I0 D 2 = Q 2 ’Q 1 ’ D 2 = Q 1 ’ Q1Q1 Asgn #1 Asgn #3

92 CMPUT Computer Organization and Architecture II92 D 1 Equations for Asgn #3 Q0Q0 1 X XX 1 X1 XX Q2Q2 I0I0 Q1Q1 D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #3

93 CMPUT Computer Organization and Architecture II93 Comparing D 1 Equation for Asgn #3 and Asgn #1 Q0Q0 1 X XX 1 X1 XX Q2Q2 I0I0 Q1Q1 D 1 = Q 2 + Q 0 + Q 1 ’ Q0Q0 1 XX 1 11 XX 1X 1 X 1 Q2Q2 I0I0 Q1Q1 D 1 = Q 2 + Q 0 + Q 1 ’I 0 D 2 = Q 1 ’ Asgn #3 Asgn #1

94 CMPUT Computer Organization and Architecture II94 D 0 Equations for Asgn #3 Q0Q0 1 X XX X XX 1 1 Q2Q2 I0I0 Q1Q1 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #3

95 CMPUT Computer Organization and Architecture II95 Comparing D 0 Equation for Asgn #3 and Asgn #1 Q0Q0 1 X XX X XX 1 1 Q2Q2 I0I0 Q1Q1 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ Q0Q0 XX 1 XX XX 1 Q2Q2 I0I0 Q1Q1 D 0 = Q 2 I 0 D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #3 Asgn #1

96 CMPUT Computer Organization and Architecture II96 Z 0 Equations for Asgn #3 Q0Q0 X XX 1 1 Q1Q1 Q2Q2 Z 0 = Q 2 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #3

97 CMPUT Computer Organization and Architecture II97 Comparing D 0 Equation for Asgn #3 and Asgn #1 Q0Q0 X XX 1 1 Q1Q1 Q2Q2 Z 0 = Q 2 1 XX X 1 Q1Q1 Q2Q2 Q0Q0 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #3 Asgn #1

98 CMPUT Computer Organization and Architecture II98 Z 1 Equations for Asgn #3 Q0Q0 X XX 11 Q1Q1 Q2Q2 Z 1 = Q 0 Z 0 = Q 2 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #3

99 CMPUT Computer Organization and Architecture II99 Comparing D 0 Equation for Asgn #3 and Asgn #1 Q0Q0 X XX 11 Q1Q1 Q2Q2 Z 1 = Q 0 Z 0 = Q 2 Z 1 = Q 0 + Q 2 Q 1 ’ Q0Q0 1 XX 1X Q1Q1 Q2Q2 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 1 ’ Asgn #1 Asgn #3

100 CMPUT Computer Organization and Architecture II100 State and Output Equations for Asgn #3 Z 1 = Q 0 Z 0 = Q 2 D 0 = Q 2 I 0 + Q 1 ’ I 0 ’ D 1 = Q 2 + Q 0 + Q 1 ’ D 2 = Q 2 ’Q 1 ’

101 CMPUT Computer Organization and Architecture II101 Comparing Equations for Asgns #1, #2, and #

102 CMPUT Computer Organization and Architecture II102 State of the Art for State Assignment G. De Micheli, R. K. Brayton, and A. Sangiovanni- Vicentelli, “Optimal State Assignment for Finite State Machines,” IEEE Transactions on Computer Aided Design of Integrated Circuit Systems, vol. 4, pp , July S. Devadas, H.-K. T. Ma, A. R. Newton, and A. Sangiovanni-Vicentelli, “Mustang: State Assignment of finite state machines for optimal multi-level logic implementations,” in International Conference on Computer Aided Design, pp , (KISS - Keep Internal State Simple)

103 CMPUT Computer Organization and Architecture II103 State of the Art for State Assignment D. Varma and E. A. Trachtenberg, “A fast algorithm for the optimal assignment of large finite state machines,” in International Conference on Computer Aided Design, pp , T. Villa and A. Sangiovanni-Vicentelli, “NOVA: State assignment of finite state machines for optimal two-level logic implementation,” IEEE Transactions on Computer Aided Design of Integrated Circuit Systems, vol. 9, pp , Sept

104 CMPUT Computer Organization and Architecture II104 Where to find papers? To find papers on the subject, search for the keyword “state assignment” in citations of the site: You can use this site for any subject of your interest within Computing Science.


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