Presentation is loading. Please wait.

Presentation is loading. Please wait.

ITEC 352 Lecture 22 Pipelining. Review Questions? Homework 3 due next Wed. Control units for RISC Pipeline –Why? Problems? Video.

Similar presentations


Presentation on theme: "ITEC 352 Lecture 22 Pipelining. Review Questions? Homework 3 due next Wed. Control units for RISC Pipeline –Why? Problems? Video."— Presentation transcript:

1 ITEC 352 Lecture 22 Pipelining

2 Review Questions? Homework 3 due next Wed. Control units for RISC Pipeline –Why? Problems? Video

3 Pipelining Outline Pipelining –Problems –Branching –Performance

4 Pipelining Example Pipelining is not always efficient. Sometimes an instruction depends on its previous instruction’s results. –Implement the pipeline for the following: srl %r3, %r5 addcc %r1, 10, %r1 ld %r1, %r2 subcc %r2, %r4, %r4 E.g., CPUcycle Unit1 Unit2 Unit3 Unit4 Unit5 © Prem Uppuluri, Derived from Doug Comer

5 Pipelining More problems Another major problem: branch instructions. –E.g., consider the following program snippet: addcc %r1, %r2, %r3 be done srl %r1, 10, %r1 ba done2 done: sll %r1, 10, %r1 done2: halt. Can you see why the instructions cannot execute in 1 cpu cycle…draw the pipeline diagram

6 Pipelining Branches Branch instructions thus cause the pipeline to be flushed. Usually, after a branch a bunch of NOPs (no operations) are filled. Similar problem with load (ld) and store (st). Since these instructions access the memory (which is slow to access), they need additional cycles (usually 1 additional cycle).

7 Pipelining Load/store The extra cycles for load and store are called delayed loads/stores. Any solutions to the branch problem? –Speculative branches. –One approach: load the next instruction after branch. If however, the branch fails, then undo the damage….

8 Pipelining ILP: another issue. ILP is great, because it is transparent to programmers…. –As a programmer you do not have to instruct the CPU to perform pipelining. However, you could destroy the efficiency or get incorrect results …. This is called pipeline hazard E.g., consider the following two lines of code: inst1: addcc %r1, 10, %r1 inst2: ld %r1, %r2 Can you see any problems with these two instructions in a pipleline? Slide example taken verbatim from Doug Comer: Essentials of Computer Architecture

9 Pipelining ILP: another issue. ILP is great, because it is transparent to programmers…. –As a programmer you do not have to instruct the CPU to perform pipelining. However, you could destroy the efficiency or get incorrect results …. This is called pipeline hazard E.g., consider the following two lines of code: inst1: addcc %r1, 10, %r1 inst2: ld %r1, %r2 Problem: The second “ld” instruction uses operand r1, which it will get only after the first instruction “addcc” is executed. Slide example taken verbatim from Doug Comer: Essentials of Computer Architecture

10 Pipelining Programmer consequences Reorder instructions when necessary. E.g., C = A+B D = E-C F = G+H J = I-F M = K+L P = M-N How will you reorder? Slide example taken verbatim from Doug Comer: Essentials of Computer Architecture

11 Pipelining Answer Reorder instructions when necessary. E.g., C = A+B D = E-C F = G+H J = I-F M = K+L P = M-N C = A+B F = G+H M = K+L D = E-C J = I-F P = M-N Slide example taken verbatim from Doug Comer: Essentials of Computer Architecture

12 Pipelining Pipeline efficiency Efficiency of a pipeline is given by a value: CPI avg = average cycles per instruction. Ideally, CPIavg = 1. Why? –We want to execute one instruction per one clock cycle. What if a branch is taken?

13 Pipelining Branch Let, –b : branch penality (i.e., the number of cycles lost because of a branch). Usually this is 4 (4 cycles are lost). –P b : probability of an instruction being a branch –CPI nobranch = no branch taken. = 1 Then, CPI avg = (1 – P b ) (CPI nobranch ) + Pb(b) = 1 + bPbPt Example; probability a branch is taken: 0.25, b = 4 What is CPIavg?

14 Pipelining Speculative pipelining Let, –b : branch penality (i.e., the number of cycles lost because of a branch). Usually this is 4 (4 cycles are lost). –P b : probability of an instruction being a branch –P t : probability that a branch is taken (when using speculative pipelining). –CPI nobranch = no branch taken. = 1 Then, CPI avg = (1 – P b ) (CPI nobranch ) + P b (P t (CPI nobranch ) + (1-P t ) b)) Example; probability a branch is taken: 0.25, b = 4, P t =.5. What is CPIavg?

15 Pipelining Execution Efficiency Any processors execution efficiency is given as the ratio of CPI nobranch /CPI avg.

16 Pipelining Next … We are done with Assembly. –Next: Memory (Chapter 7)

17 Pipelining Review Pipelining


Download ppt "ITEC 352 Lecture 22 Pipelining. Review Questions? Homework 3 due next Wed. Control units for RISC Pipeline –Why? Problems? Video."

Similar presentations


Ads by Google