# L 18 : Circuit Level Design 성균관대학교 조 준 동 교수

## Presentation on theme: "L 18 : Circuit Level Design 성균관대학교 조 준 동 교수"— Presentation transcript:

L 18 : Circuit Level Design 성균관대학교 조 준 동 교수 http://vlsicad.skku.ac.kr

Buffer Chain Delay analysis of buffer chainDelay analysis considering parasitic capacitance,C p Ck,Pk: stage k buffer output 의 total capacitance, power PT: buffer chain 의 power consumption Pn: load capacitance CL 의 power consumption Eff: power efficiency pn/pT

Slew Rate Determining rise/fall time

Slew Rate(Cont’d) Power consumption of Short circuit current in Oscillation Circuit

Pass Transistor Logic Reducing Area/Power –Macro cell(Large part in chip area)  XOR/XNOR/MUX(Primitive)  Pass Tr. Logic –Not using charge/discharge scheme  Appropriate in Low Power Logic Pass Tr logic Family –CPL (Complementary Pass Transistor Logic) –DPL (Dual Pass Transistor Logic) –SRPL (Swing Restored Pass Transistor Logic) CPL –Basic Scheme –Inverter Buffering

Pass Transistor Logic(Cont’d) DPL –Pass Tr Network + Dual p-MOS –Enables rail-to-rail swing –Characteristics Increasing input capacitance(delay) Increasing driving ability for existing 2 ON-path equals CPL in input loading capacitance SRPL –Pass Tr network + Cross coupled inverter –Restoring logic level –Inverter size must not be too big

Dynamic Logic Using Precharge/Evaluation scheme Family –Domino logic –NORA(NO RAce) logic Characteristics –Decreasing input loading capacitance –Power consumption in precharge clock –Increasing useless switching in precharging period Basic architecture of Domino logic

Input Pin Ordering Reorder the equivalent inputs to a transistor based on critical path delays and power consumption N- input Primitive CMOS logic –symmetrical in function level –antisymmetrical in Tr level capacitance of output stage body effect Scheme –The signal that has many transition must be far from output –If it is hard to estimate switching frequency, we must determine pin ordering considering path and path delay balance from primary input to input of Tr. Example of N-input CMOS logic Experimentd with gate array of TI For a 4-input NAND gate in TI’s BiCMOS gate array library (with a load of 13 inverters), the delay varies by 20% while power dissipation by 10% between a good and bad ordering

INPUT PIN Reordering Simulation result ( t cycle =50ns, t f /t r =1ns) : A 가 critical input 인 경우 =38.4uW, D 가 critical input 인 경우 =47.2uW

Sensitization Example Definition –sensitization : input signal that forces output transition event –sensitization vector : the other inputs if one signal is sensitized

Sensitization(Cont’d) Considering Sensitization in Combinational logic:Remove unnecessary transitions in the C.L Considering Sensitization in Sequential logic: Also reduces the power consumption in the flip- flops.

TTL-Compatible TTL level signal  CMOS input Characteristic Curve of CMOS Inverter

TTL Compatible(Cont’d) CMOS output signal  TTL input –Because of sink current I OL, CMOS gets a large amount of heat –Increased chip operating temperature –Power consumption of whole system

INPUT PIN Reordering ◈ To reduce the power dissipation one should place the input with low transition density near the ground end. (a) If MNA turns off, only CL needs to be charged (b) If MND turns off, all CL, CB, CC and CD needs to be charged (c) If the critical input is rising and placed near output node, the initial charge of C B, C C and C D are zero and the delay time of C L discharging is less than (d) (d) If the critical input is rising and placed near ground end, the charge of CB, CC and CD must dischagge before the charge of CL discharge to zero

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