1. Microarchitecture of Superscalars (7) Preserving sequential consistency Dezső Sima Fall 2007 (Ver. 2.0)  Dezső Sima, 2007

2. Overview 1. The processor consistency 2. The Reorder Buffer 3. The introduction of the ROB

3. Overview 1 The processor consistency 2 The Reorder Buffer 3 The introduction of the ROB

4. Processor consistencyMemory consistency Sequential consistency of instruction execution Consistency of the sequence of instruction completions Consistency of the sequence of memory accesses 1. Processor consistency (1)

5. Weak processor consistency Strong processor consistency Detection and resolution Power1 POWER2 (1990) (1993) Processor consistency Instructions may complete out-of-order, only if no dependences are injured Instructions complete strictly in program order Instruction reordering is allowed No instruction reordering is allowed of dependences ensures weak processor consistency ROB ensures strong processor consistency 88110 PPC 601 (1991) (1993) -line R8000(1994)  ES/9000 PPC 602-620 (1992p) Pentium Pro UltraSPARC (1995) K5(1995) PA 8000 R 10000 (1996) Trend 1. Processor consistency (2) (till 21264)

6. 2. The Reorder Buffer (1) Introduction: Smith and Pleszkun (1988) Figure 2.1: The principle of the ROB A subsequent ROB-entry is allocated 24 25 8 Tail pointer (T) (identifies the next instruction to each dispatched instruction in-order 0 1 31 Head pointer (H) dispatched instruction) Instructions retire in-order and modify the program state Free entries Instructions in processing to be retired) (identifies the last Status codes: in processing finished An instruction pointed to by the Tail pointer retires if all previous instructions are already retired and 7 the instruction considered is finished.

7. 2. The Reorder Buffer (2) Figure 2.2: The principle of the ROB while supporting speculative execution Tail pointer (T) (next instruction to be retired) Head pointer (H) Free entries Instructions in processing (last occupied entry) Status codes: in processing finished speculative not speculative 24 25 8 0 1 31 7 A subsequent ROB-entry is allocated to each dispatched instruction in-order An instruction pointed to by the Tail pointer retires if all previous instructions are already retired, the instruction considered is finished and Instructions retire in-order and modify the program state it is not in the speculative state.

8. 2. The Reorder Buffer (3) Figure 2.3: The operation of the ROB during dispatching two instructions 24 25 8 0 1 31 Entry 25: add r1, r2, r3 26: sub r4, r1, r5 26 T H Instructions in processing 7

9. 2. The Reorder Buffer (4) Figure 2.4: The operation of the ROB during execution Status reports 24 25 8 0 1 31 26 send status reports (in some cases also results) to the allocated ROB entries During execution instructions T H Instructions in processing 7

10. 2. The Reorder Buffer (5) Figure 2.5: The operation of the ROB during retirement Instruction corresponding to entry 8 retires and modifies program state 9 Next instruction to be retired is the one associated with entry 9. 24 25 8 0 1 31 26 Retirement if the instruction considered is finished and it is not in the speculative state all previous instructions already retired, T H Instructions in processing 7

11. 2. The Reorder Buffer (5) Figure 2.5: The operation of the ROB during retirement Instruction corresponding to entry 8 retires and modifies program state 9 Next instruction to be retired is the one associated with entry 9. 24 25 8 0 1 31 26 Retirement if the instruction considered is finished and it is not in the speculative state all previous instructions already retired, T H Instructions in processing 7

12. 3. The introduction of the ROB Figure 3.1: The introduction of the ROB