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Copyright © 2008 All rights reserved 0 從一串鞭炮到 ESL Alan P. Su Global Unichip Corp.

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Presentation on theme: "Copyright © 2008 All rights reserved 0 從一串鞭炮到 ESL Alan P. Su Global Unichip Corp."— Presentation transcript:

1 Copyright © 2008 All rights reserved 0 從一串鞭炮到 ESL Alan P. Su Global Unichip Corp.

2 Copyright © 2008 All rights reserved 1 1 Curriculum Vitae Alan P. Su received his bachelor degree in computer science from Chung-Yuan Christian University in 1986. After working as a system analyst with CMS (later EDS Taiwan and now HP), he went to the States and received M.S. degree from University of Missouri Rolla in 1994 and doctorate from University of California Riverside in 1998. Between 1998 and 2002 he worked for EEsof, Hewlett-Packard Company, later spun off to become Agilent, to develop a DSP Synthesis tool and other Electronic System Level (ESL) tools. In 2003 he returned to Taiwan and joined SoC Technology Center, ITRI to conduct several ESL projects in tool development, SoC designing and design methodologies. While remained as a consultant with ITRI, in April 2006 he joined SpringSoft, Inc. to lead the development of ESL tools. In August 2008 he joined Global Unichip Corp. to develop ESL development boards as platforms to provide ESL design services. Dr. Su involves in various ESL standardization efforts. He is a member of OSCI Transaction Level Modeling (TLM) Working Group, Synthesis Working Group, Configuration, Control and Inspection Working Group, Language Working Group and OCP-IP Debug Working Group. He is also the Chair of Taiwan SystemC Users Group. Dr. Su's research interest includes distributed and parallel computing, leakage current minimization, 3D IC and ESL verification, synthesis, debug, testing and design methodologies.

3 Copyright © 2008 All rights reserved 2 2 一串鞭炮 Alan P. Su received his bachelor degree in computer science from Chung-Yuan Christian University in 1986.

4 Copyright © 2008 All rights reserved 3 3 兩台機器 After working as a system analyst with CMS (later EDS Taiwan and now HP),…

5 Copyright © 2008 All rights reserved 4 4 三個專題 …he went to the States and received M.S. degree from University of Missouri Rolla in 1994…

6 Copyright © 2008 All rights reserved 5 5 Parallel Computing  Using a parallel computer to speed up the computation.  Parallel computer: multiple processing elements interconnected in a specific architecture and controlled by a general purpose processor.  Architecture examples: hyper cube, mesh, ring, pyramid, etc.

7 Copyright © 2008 All rights reserved 6 6 Example Parallel Architectures2 2323 2424 2121 Hyper Cube Mesh+ Ring Ring For each application, e.g. sorting, they all have specific and different ways to implement. The implementation takes advantage of the architecture to speed up the application.

8 Copyright © 2008 All rights reserved 7 7 Distributed Computing  Deploy an application on inter- connected computers to tolerate fault thus increase the service quality.  Internet is an implementation of such concept.  Lots of distributed computing research focus on software engineering, including formal proving.

9 Copyright © 2008 All rights reserved 8 8 Grid Computing  It is distributed computing in the bone.  However many researchers today use grid to compute a big problem in parallel.  Grid blurs the line between parallel and distributed computing. And the term “ concurrent computing ” maybe more appropriate.

10 Copyright © 2008 All rights reserved 9 9 SoC Multi-Core Platform  Currently it is implemented in the mindset of distributed computing without the intent of fault tolerance.  Heterogeneous cores and multi- threaded computing.  Resource tracing is the main issue in today ’ s verification and debug needs.

11 Copyright © 2008 All rights reserved 10 Dining Philosopher Problem  Multi-Process Synchronization  Each philosopher think and eat  Must have two forks, or chopsticks, to eat  Deadlock occurs if must pick right hand fork first, and when all philosophers come to eat at the same time

12 Copyright © 2008 All rights reserved 11 Dining Philosopher Solutions  Solution 1: Not all philosophers can eat at the same time  Solution 2: Number chopsticks from small to large in order. A philosopher must take smaller number chopstick first.

13 Copyright © 2008 All rights reserved 12 Cheating Husbands Puzzle*  Mamajorca, Atlantis, a country ruled by women.  Only after proven as a perfect logician a woman could marry.  The queen, Henrietta I, gathered all married women in the town square one day and announced that: There are one or more cheating husbands. You know all other cheating husbands but your own. No discussions allowed. On the day you can determine your husband is cheating on you, shoot him at midnight. 39 silent nights went by. On 40 th night, shots were heard. How many shots? Or how many cheating husbands? * Y. Moses, D. Dolev and J.Y. Halpern, “ Cheating Husbands and Other Stories: A Case Study of Knowledge, Action, and Communication". Distributed Computing (1986) 1: 167 – 176.

14 Copyright © 2008 All rights reserved 13 40 Cheating Husbands Were Killed!  Proved by induction: 1 cheating husband: the cheated wife, who know no other cheating husbands, kill that SoB the first midnight. Assume this is true for N cheating husbands that they were shot on N th midnight. N+1 cheating husbands: the first N nights the N+1 wives knew N cheating husband didn ’ t shoot. When heard no shots the first N nights they immediately knew their husbands were cheating and kill them on the N+1 th midnight.

15 Copyright © 2008 All rights reserved 14 Henrietta II, The Disgraced  Henrietta II installed a mail system so no town square gathering was required. The mail system guaranteed that mails would reach receivers eventually. She sent out a first mail to announce this mail system, then sent the second letter, exactly the same as her mother ’ s announcement.  No husbands were killed because of asynchronous communication system puzzled wives if other cheated wives received the message yet. P.S. If there was only one cheating husband then it would work.

16 Copyright © 2008 All rights reserved 15 Queen Margaret  Killed all cheating husbands in 3 days, with a strongly synchronized communication system, and allow shooting into the air.  Well, how so? Please read the paper.

17 Copyright © 2008 All rights reserved 16 Future Multi-Core SoC ’ s  In the near future true parallel computing will be employed by constructing a specialized parallel architecture. Like IBM Cell processor and Intel 80-core processor.  Speed-up factor analysis (against # of PE ’ s) and bottleneck analysis (to find why the speed-up is not as expected) are needed.

18 Copyright © 2008 All rights reserved 17 Electronic Design Automation …and doctorate from University of California Riverside in 1998.

19 Copyright © 2008 All rights reserved 18 EDA  Software tools that help designers to design, implement and verify electronic devises.  Examples: Math Modeler, RF Simulation, architecture synthesis, behavior synthesis, logic synthesis, place & route, pSpice, etc.  Almost all the problems to be solved in EDA are either NP complete or NP hard.

20 Copyright © 2008 All rights reserved 19 在大學沒學好的東西 Gate SourceDrain V DD Ground Leakage Current

21 Copyright © 2008 All rights reserved 20 在大學沒學好的東西 Gate SourceDrain V DD Ground Leakage Current V DD Ground Out PMOS NMOS CMOS Inverter In 0101

22 Copyright © 2008 All rights reserved 21 在大學沒學好的東西 Gate SourceDrain V DD Ground 靜電防護 Electrostatic Discharge, ESD Leakage Current

23 Copyright © 2008 All rights reserved 22 一個有游泳池的家 Between 1998 and 2002 he worked for EEsof, Hewlett-Packard Company, later spun off to become Agilent, to develop a DSP Synthesis tool and other Electronic System Level (ESL) tools.

24 Copyright © 2008 All rights reserved 23 System-on-a-Chip (SoC)  Key word: System  System an assemblage or combination of things or parts forming a complex or unitary whole, Random House Webster’s College Dictionary, p.1329  Embedded System is a special-purpose system in which the computer (processor) is completely encapsulated by the device it controls, Wikipedia

25 Copyright © 2008 All rights reserved 24 A Single Core Design ARM Core AHB USB APB (0x2054, 0x3F, Cycle 3552) (0x3002054, 0x3F, Cycle 3550) 13 14 15 16 17 Cycle 3540 DMAC

26 Copyright © 2008 All rights reserved 25 Message Passing via Shared Memory ARM Core AHB0AHB1 WR (0x2054, 0x3F, Cycle 3552) WR (0x3002054, 0x3F, Cycle 3550) 13 14 15 16 17 Cycle 3540 DSP Core RD (0x1002054, 0x3F, Cycle 3764) ICM 35 36 37 38 39 RD (0x2054, 0x3F, Cycle 3766) Cycle 3760 RAM

27 Copyright © 2008 All rights reserved 26 A Multi-Core, Multi-Thread Application ARM Core AHB0AHB1 DSP Core ICM RAM LCD Display APB 73 74 75 76 77 35 36 37 38 39 WR Tx [3270, 3380] RD Tx [3450, 3570] Interrupt 123123 ISR AP1OSAP2 AP1AP2Display USB 13 14 15 16 17 Data Task Graph

28 Copyright © 2008 All rights reserved 27 事業第二春 In 2003 he returned to Taiwan and joined SoC Technology Center, ITRI to conduct several ESL projects in tool development, SoC designing and design methodologies.

29 Copyright © 2008 All rights reserved 28 IBM Cell Processor

30 Copyright © 2008 All rights reserved 29 Intel 80-Core

31 Copyright © 2008 All rights reserved 30 Media-Oriented Systems Transport - MOST

32 Copyright © 2008 All rights reserved 31 國標 Dr. Su involves in various ESL standardization efforts. He is a member of OSCI Transaction Level Modeling (TLM) Working Group, Synthesis Working Group, Configuration, Control & Inspection Working Group, Language Working Group and OCP-IP Debug Working Group. He is also the Chair of Taiwan SystemC Users Group.

33 Copyright © 2008 All rights reserved 32 SoC Design Challenges  Moore ’ s Law and More than Moore  Architecture design and exploration Lower cost and power Faster and smaller  Verification Top-down reusable test benches Reliable early stage verification  Shorter & shorter turn-around 10M gates in 3 months or less

34 Copyright © 2008 All rights reserved 33 Electronic System Level ESL is a solution to SoC design challenges. Definition: The use of appropriate abstractions in order to increase comprehension of a system, and to enhance the probability of successfully implementing its functionality in a cost effective manner, while meeting necessary constraints. “ESL Design and Verification”, Bailey, Martin & Piziali, 2007

35 Copyright © 2008 All rights reserved 34 ESL Design Methodology Macro Architecture Exploration & Verification Micro Architecture Exploration & Verification

36 Copyright © 2008 All rights reserved 35 TLM 2.0  An Architecture Exploration Standard Untimed (UT): algorithm verification Loosely timed (LT): macro architecture exploration Approximately timed (AT)  macro architecture verification  micro architecture exploration Cycle accurate (CA, not implemented by OSCI yet): micro architecture verification

37 Copyright © 2008 All rights reserved 36 Adopting ESL What you should be doing today

38 Copyright © 2008 All rights reserved 37 Need 1: ESL/FPGA Co-Emulation Specification Algorithm Analysis Data Flow Analysis ESL/FPGA Co-Emulation  Legacy RTL IP Reuse  TLM 2.0 Modeling  Architecture Design  Hybrid ESL Verification  Performance Analysis  ESL IP Verification ESL Verification High Level Synthesis RTL Coding ESL/FPGA Regression Test Architecture Design

39 Copyright © 2008 All rights reserved 38 Need 2: ESL Verification  Conventional RTL Design Verilog Target Simulation C++ Developed & Verified C++ Test Vectors Verilog Test Vectors FPGA Target Emulation FPGA Reduced Test Vectors  ESL/FPGA RTL Design FPGA Target Emulation C++ Developed & Verified C++ Test Vectors Verilog Target Simulation Verilog Test Vectors SCV TLM 2.0 Functional plus Formal Verification

40 Copyright © 2008 All rights reserved 39 Need 3: HLS with ESL Verification High Level Synthesis FPGA Target Emulation C++ Algorithms C++ Test Harness HDL Target Simulation HDL Test Vectors Functional plus Formal Verification Logic Bugs Identified Debug SCV TLM 2.0 Fast Regression Test 2 to 3 Orders Faster than Simulation

41 Copyright © 2008 All rights reserved 40 Issues to Focus  Enhance Design Productivity and Quality Close the gap between IC Density and Design Productivity Design flow integration  ESL Verification Reuse algorithm level test suite High-level models for architectural verification at early stage ESL/FPGA co-emulation, faster and easier  High Level Synthesis (HLS) Productivity Boost Architecture Exploration Control Intensive & communication interface  Multi-Core Design Identify the architecture with lowest cost and power Early stage software development support Multi-core HW/SW co-debug

42 Copyright © 2008 All rights reserved 41 命運真奇妙 Dr. Su's research interest includes distributed and parallel computing, leakage current minimization, and ESL verification, synthesis, debug, testing and design methodology.

43 Copyright © 2008 All rights reserved 42 Q & A


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