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Gigabit Ethernet Group 1 Harsh Sopory Kaushik Narayanan Nafeez Bin Taher.

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Presentation on theme: "Gigabit Ethernet Group 1 Harsh Sopory Kaushik Narayanan Nafeez Bin Taher."— Presentation transcript:

1 Gigabit Ethernet Group 1 Harsh Sopory Kaushik Narayanan Nafeez Bin Taher

2 Background Information An introduction to Gigabit Ethernet

3 What Is Ethernet? Most successful LAN technology Most successful LAN technology Operates at the Data Link Layer (layer 2) of the OSI reference model Operates at the Data Link Layer (layer 2) of the OSI reference model Acts as an interface between the MAC layer and transceivers in Ethernet hardware (Physical layer) Acts as an interface between the MAC layer and transceivers in Ethernet hardware (Physical layer) Uses contention based medium access protocol – CSMA/CD Uses contention based medium access protocol – CSMA/CD

4 Gigabit Ethernet Builds on top of the Ethernet protocol Builds on top of the Ethernet protocol Allows data transfer speeds of 1000 Mbps Allows data transfer speeds of 1000 Mbps Provides reliable communication between applications of the Network and Transport layers Provides reliable communication between applications of the Network and Transport layers

5 IEEE Gigabit Ethernet Specifications 802.3z 1000BASE-CX (short- haul copper) 1000BASE-CX (short- haul copper) 1000BASE-LX (long- wavelength optics) 1000BASE-LX (long- wavelength optics) 1000BASE-SX (short- wavelength optics) 1000BASE-SX (short- wavelength optics) 802.3ab 1000BASE-T (twisted pair) 1000BASE-LH (long- haul)

6 Benefits of Gigabit Ethernet Higher data transfer rates Higher data transfer rates Builds on current Ethernet Builds on current Ethernet Familiar technology Familiar technology Minimal staff training Minimal staff training

7 Project Proposal Our aim and immediate goals

8 Project Aim Main Issue: High costs associated with installing Gigabit Ethernet technology Main Issue: High costs associated with installing Gigabit Ethernet technology A source of high cost: Opto-electronic transceiver module A source of high cost: Opto-electronic transceiver module Project Aim: Design cheaper module Project Aim: Design cheaper module

9 Immediate Goals Set up test bed for future use Set up test bed for future use Test module on evaluation board to confirm Gigabit transfer rates Test module on evaluation board to confirm Gigabit transfer rates Test module with Gigabit Ethernet card to confirm successful data transfer Test module with Gigabit Ethernet card to confirm successful data transfer

10 Brief Description of Module Agilent HFBR 53D5 Agilent HFBR 53D5 Consists of transmitter and receiver sections Consists of transmitter and receiver sections Transmitter section consists of an 850 nm VCSEL in an Optical Sub Assembly (OSA) Transmitter section consists of an 850 nm VCSEL in an Optical Sub Assembly (OSA) Receiver consists of a Si PIN diode mounted on the OSA with a transimpedance preamplifier IC Receiver consists of a Si PIN diode mounted on the OSA with a transimpedance preamplifier IC Signal Detect circuitry provided Signal Detect circuitry provided

11 Design Steps and Considerations Our design approach

12 Design Steps Construct Evaluation Board Construct Evaluation Board Remove Transceiver from card Remove Transceiver from card Place components and Transceiver on Board Place components and Transceiver on Board Test Board Test Board Connect Board to Gigabit Card Connect Board to Gigabit Card Test setup with another Gigabit Card Test setup with another Gigabit Card

13 Agilent Schematic The evaluation board that Agilent provides for testing the module is schematically represented below The evaluation board that Agilent provides for testing the module is schematically represented below

14 Georgia Tech Evaluation Board In order to reduce costs, a GA Tech evaluation board was used and is shown below In order to reduce costs, a GA Tech evaluation board was used and is shown below

15 Circuit Schematic All parts from the Agilent design were not necessary and the circuit layout used is shown below All parts from the Agilent design were not necessary and the circuit layout used is shown below

16 Primary Design Considerations Power Supply Filtering Circuit Power Supply Filtering Circuit Transmission Lines and Terminations Transmission Lines and Terminations

17 Power Supply Filtering Circuit Agilent Board: Circuit was included to keep both parts of the transceiver independent of their power supply considerations Agilent Board: Circuit was included to keep both parts of the transceiver independent of their power supply considerations Our Board: Eliminated the need for the circuit by having two separate power supplies for both parts of the module Our Board: Eliminated the need for the circuit by having two separate power supplies for both parts of the module

18 Transmission Lines and Terminations Transmission lines were eliminated from our boards Transmission lines were eliminated from our boards –Care was taken to keep the length of the lines less than 1/10 th the signal wavelength i.e. 6 cm –Sharp angles on the board were avoided

19 Miscellaneous Considerations Reduce susceptibility to noise Reduce susceptibility to noise –Accomplished by using differential inputs as opposed to single-ended ones Top and bottom of board unconnected Top and bottom of board unconnected –Used vias to connect the two

20 Component Details Capacitors mainly used for Decoupling Capacitors mainly used for Decoupling –Capacitors used to separate power supplies from circuit. –Protect circuits from transients Resistors used for terminations and biasing Resistors used for terminations and biasing

21 Problems Faced Soldering Soldering –surface mount components Top and Bottom of board unconnected Top and Bottom of board unconnected –Power not getting through from one side to another –Solved by allowing solder to drip through to form a connection

22 Connecting Card to Board Used RG174 Cable with SMA connectors to connect card to board Used RG174 Cable with SMA connectors to connect card to board Removed resistor networks from Gigabit card Removed resistor networks from Gigabit card Used wire to connect signal detect pin from board to card Used wire to connect signal detect pin from board to card Connected the grounds of board and card with wire Connected the grounds of board and card with wire

23 Test Layout Resistor networks removed

24 Results Eye diagrams and bit error rate data

25 Board Test Setup Power Ch1 Oscilloscope Pattern Generator Ch2 Oscilloscope Pattern Generator Fiber Optic Cable RX TX

26 Eye diagram for 10m Cable

27 Eye diagram for 100m Cable

28 Significance of Eye Diagram Eye formed by superimposition of pseudorandom bit patterns Eye formed by superimposition of pseudorandom bit patterns Eye generated met standard specifications Eye generated met standard specifications –Indicated signal quality was acceptable Standard Eye MaskSuperimposed Eye Mask

29 Bit Error Rate Data 10m cable: No errors encountered 10m cable: No errors encountered 100m cable: No errors encountered 100m cable: No errors encountered Errors appeared when using PN23 encoding scheme at 1.2 Gbps Errors appeared when using PN23 encoding scheme at 1.2 Gbps –Error rate = 2.3 errors/Mb

30 Verification of results Card was plugged into computer Card was plugged into computer Passed loop-back diagnostic test Passed loop-back diagnostic test Connected to another computer using fiber optic cable Connected to another computer using fiber optic cable Packets sent and received with no errors Packets sent and received with no errors File transferred successfully over link File transferred successfully over link

31 Computers on LAN

32 Summary The card was assembled and tested successfully The card was assembled and tested successfully Questions? Questions? –Harsh Sopory (gte648h) –Kaushik Narayanan (gte678h) –Nafeez Bin Taher (gte078h)


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