Presentation on theme: "Carnegie Mellon 1 Saint Louis University Storage Technologies and Memory Hierarchy CSCI 224 / ECE 317: Computer Architecture Instructor: Prof. Jason Fritts."— Presentation transcript:
Carnegie Mellon 1 Saint Louis University Storage Technologies and Memory Hierarchy CSCI 224 / ECE 317: Computer Architecture Instructor: Prof. Jason Fritts Slides adapted from Bryant & O’Hallaron’s slides
Carnegie Mellon 2 Saint Louis University Storage Technologies and Memory Hierarchy Storage Technologies and Trends RAM Nonvolatile memory Disk Trends Locality, Cache, and Memory Hierarchy to the Rescue!
Carnegie Mellon 3 Saint Louis University Random-Access Memory (RAM) Basic storage unit is normally a cell (one bit per cell). Static RAM (SRAM) Each cell stores a bit with a four or six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Dynamic RAM (DRAM) Each cell stores bit with a capacitor; one transistor used for access Value must be refreshed every 10-100 ms Trans.AccessNeeds per bit timerefresh?CostApplications SRAM4 or 6 1X No100xCache memories DRAM 1 10X Yes 1XMain memories, frame buffers
Carnegie Mellon 4 Saint Louis University Conventional DRAM Organization D x W DRAM: organized as D supercells of size W bits access desired supercell by first sending row address (RAS), then column address (CAS) 16 x 8 DRAM chip Cols Rows 0 123 0 1 2 3 Internal row buffer CAS = 1 addr data 2/2/ 8/8/ Memory controller supercell (2,1) supercell (2,1) To CPU RAS = 2
Carnegie Mellon 5 Saint Louis University Memory Modules : supercell (i,j) 64 MB memory module consisting of eight 8Mx8 DRAMs addr (row = i, col = j) Memory controller DRAM 7 DRAM 0 03178151623243263394047485556 64-bit doubleword at main memory address A bits 0-7 bits 8-15 bits 16-23 bits 24-31 bits 32-39 bits 40-47 bits 48-55 bits 56-63 64-bit doubleword 03178151623243263394047485556
Carnegie Mellon 6 Saint Louis University Enhanced DRAMs Basic DRAM cell has not changed since its invention in 1966 Commercialized by Intel in 1970 DRAM cores with better interface logic and faster I/O : Synchronous DRAM (SDRAM) Uses a conventional clock signal instead of asynchronous control Double data-rate synchronous DRAM (DDR SDRAM) Double edge clocking sends two bits per cycle per pin Different types distinguished by size of small prefetch buffer: –DDR (2 bits), DDR2 (4 bits), DDR3 (8 bits) DDR RAM standard for most server and desktop systems
Carnegie Mellon 7 Saint Louis University Storage Technologies and Memory Hierarchy Storage Technologies and Trends RAM Nonvolatile memory Disk Trends Locality, Cache, and Memory Hierarchy to the Rescue!
Carnegie Mellon 8 Saint Louis University Nonvolatile Memories DRAM and SRAM are volatile memories Data lost when powered off Nonvolatile memories retain value even if powered off Read-only memory (ROM) – programmed during production Programmable ROM (PROM) – can be programmed once Electrically-Eraseable PROM (EEPROM) – electronic erase capability Flash memory – EEPROMs with partial (sector) erase capability Wears out after about 100,000 erasings Uses for Nonvolatile Memories Firmware programs stored in a ROM (BIOS, disk controllers, …) Solid state disks (USB sticks, smart phones, tablets, laptops, …) Disk caches
Carnegie Mellon 9 Saint Louis University Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address, data, and control signals bus width in CPU defines architecture width (32-bit, 64-bit, etc.) Buses are typically shared by multiple devices Main memory I/O bridge Bus interface ALU Register file CPU chip System busMemory bus
Carnegie Mellon 10 Saint Louis University Memory Read Transaction (1) CPU places address A on the memory bus. ALU Register file Bus interface A 0 A x Main memory I/O bridge %eax Load operation: movl A, %eax CPU chip
Carnegie Mellon 11 Saint Louis University Memory Read Transaction (2) Main memory reads A from the memory bus, retrieves word x, and places it on the bus. ALU Register file Bus interface x 0 A x Main memory %eax I/O bridge Load operation: movl A, %eax CPU chip
Carnegie Mellon 12 Saint Louis University Memory Read Transaction (3) CPU read word x from the bus and copies it into register %eax. x ALU Register file Bus interface x Main memory 0 A %eax I/O bridge Load operation: movl A, %eax CPU chip
Carnegie Mellon 13 Saint Louis University Memory Write Transaction (2) CPU places data word y on the bus. y ALU Register file Bus interface y Main memory 0 A %eax I/O bridge Store operation: movl %eax, A CPU chip
Carnegie Mellon 14 Saint Louis University Memory Write Transaction (3) Main memory reads data word y from the bus and stores it at address A. y ALU y main memory 0 A %eax I/O bridge Store operation: movl %eax, A CPU chip Register file Bus interface
Carnegie Mellon 15 Saint Louis University Storage Technologies and Memory Hierarchy Storage Technologies and Trends RAM Nonvolatile memory Disk Trends Locality, Cache, and Memory Hierarchy to the Rescue!
Carnegie Mellon 16 Saint Louis University What’s Inside A Disk Drive? Spindle Arm Actuator Platters Electronics (including a processor and memory!) SCSI connector Image courtesy of Seagate Technology
Carnegie Mellon 17 Saint Louis University Disk Geometry Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. Spindle Surface Tracks Track k Sectors Gaps
Carnegie Mellon 18 Saint Louis University Tracks divided into sectors Disk Structure - top view of single platter Surface organized into tracks
Carnegie Mellon 19 Saint Louis University Disk Geometry (Muliple-Platter View) Aligned tracks form a cylinder. Surface 0 Surface 1 Surface 2 Surface 3 Surface 4 Surface 5 Cylinder k Spindle Platter 0 Platter 1 Platter 2
Carnegie Mellon 20 Saint Louis University Disk Capacity Capacity – maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB) Capacity is determined by these technology factors: Recording density (bits/in) – number of bits per segment of a track Track density (tracks/in) – number of tracks per radial segment Areal density (bits/in 2 ) – product of recording and track density Modern disks partition tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors, determined by the circumference of innermost track Each zone has a different number of sectors/track
Carnegie Mellon 21 Saint Louis University Computing Disk Capacity Capacity = (# bytes/sector) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/platter) x (# platters/disk) Example: 512 bytes/sector 300 sectors/track (on average) 20,000 tracks/surface 2 surfaces/platter 5 platters/disk Capacity = 512 x 300 x 20000 x 2 x 5 = 30,720,000,000 = 30.72 GB
Carnegie Mellon 22 Saint Louis University Disk Operation (Single-Platter View) The disk surface spins at a fixed rotational rate By moving radially, the arm can position the read/write head over any track. The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. spindle
Carnegie Mellon 23 Saint Louis University Disk Operation (Multi-Platter View) Arm Read/write heads move in unison from cylinder to cylinder Spindle
Carnegie Mellon 24 Saint Louis University Disk Access Head in position above a track
Carnegie Mellon 25 Saint Louis University Disk Access Rotation is counter-clockwise
Carnegie Mellon 26 Saint Louis University Disk Access – Read About to read blue sector
Carnegie Mellon 27 Saint Louis University Disk Access – Read After BLUE read After reading blue sector
Carnegie Mellon 28 Saint Louis University Disk Access – Read After BLUE read Red request scheduled next
Carnegie Mellon 29 Saint Louis University Disk Access – Seek After BLUE readSeek for RED Seek to red’s track
Carnegie Mellon 30 Saint Louis University Disk Access – Rotational Latency After BLUE readSeek for REDRotational latency Wait for red sector to rotate around
Carnegie Mellon 31 Saint Louis University Disk Access – Read After BLUE readSeek for REDRotational latencyAfter RED read Complete read of red
Carnegie Mellon 32 Saint Louis University Disk Access – Service Time Components After BLUE readSeek for REDRotational latencyAfter RED read Data transferSeekRotational latency Data transfer
Carnegie Mellon 33 Saint Louis University Disk Access Time Average time to access some target sector approximated by : T access = T avg seek + T avg rotation + T avg transfer Seek time (T avg seek ) Time to position heads over cylinder containing target sector. Typical T avg seek is 3—9 ms Rotational latency (T avg rotation ) Time waiting for first bit of target sector to pass under r/w head. T avg rotation = 1/2 x 1/RPMs x 60 sec/1 min Typical T avg rotation = 7200 RPMs Transfer time (T avg transfer ) Time to read the bits in the target sector. T avg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.
Carnegie Mellon 34 Saint Louis University Disk Access Time Example Given: Rotational rate = 7,200 RPM Average seek time = 9 ms. Avg # sectors/track = 400. Derived: T avg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. T avg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms T access = 9 ms + 4 ms + 0.02 ms Important points: Access time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRAM access time is about 4 ns/doubleword, DRAM about 60 ns Disk is about 40,000 times slower than SRAM, and about 2,500 times slower then DRAM
Carnegie Mellon 35 Saint Louis University I/O Bus Main memory I/O bridge Bus interface ALU Register file CPU chip System busMemory bus Disk controller Graphics adapter USB controller MouseKeyboardMonitor Disk I/O bus Expansion slots for other devices such as network adapters.
Carnegie Mellon 36 Saint Louis University Reading a Disk Sector (1) Main memory ALU Register file CPU chip Disk controller Graphics adapter USB controller mouse keyboard Monitor Disk I/O bus Bus interface CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller.
Carnegie Mellon 37 Saint Louis University Reading a Disk Sector (2) Main memory ALU Register file CPU chip Disk controller Graphics adapter USB controller MouseKeyboardMonitor Disk I/O bus Bus interface Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory.
Carnegie Mellon 38 Saint Louis University Reading a Disk Sector (3) Main memory ALU Register file CPU chip Disk controller Graphics adapter USB controller MouseKeyboardMonitor Disk I/O bus Bus interface When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special “interrupt” pin on the CPU)
Carnegie Mellon 39 Saint Louis University Solid State Disks (SSDs) Pages: 512KB to 4KB, Blocks: 32 to 128 pages Data read/written in units of pages. Page can be written only after its block has been erased A block wears out after 100,000 repeated writes. Flash translation layer I/O bus Page 0Page 1 Page P-1 … Block 0 … Page 0Page 1 Page P-1 … Block B-1 Flash memory Solid State Disk (SSD) Requests to read and write logical disk blocks
Carnegie Mellon 40 Saint Louis University SSD Performance Characteristics Why are random writes so slow? Erasing a block is slow (around 1 ms) Write to a page triggers a copy of all useful pages in the block Find an used block (new block) and erase it Write the page into the new block Copy other pages from old block to the new block Sequential read tput250 MB/sSequential write tput170 MB/s Random read tput140 MB/sRandom write tput14 MB/s Rand read access30 usRandom write access300 us
Carnegie Mellon 41 Saint Louis University Solid State Disks (SSDs) vs Rotating Disks Advantages No moving parts faster, less power, more rugged Disadvantages Have the potential to wear out Mitigated by “wear leveling logic” in flash translation layer E.g. Intel X25 guarantees 1 petabyte (10 15 bytes) of random writes before they wear out As of 2014, about 15 times more expensive per byte Applications Smart phones and tablets Found in some laptops, desktops, and servers
Carnegie Mellon 42 Saint Louis University Storage Technologies and Memory Hierarchy Storage Technologies and Trends RAM Nonvolatile memory Disk Trends Locality, Cache, and Memory Hierarchy to the Rescue!
Carnegie Mellon 43 Saint Louis University Metric1980198519901995200020052010 2010:1980 $/MB8,0008801003010.10.06 130,000 access (ns)37520010070605040 9 typical size (MB) 0.0640.256416642,0008,000 125,000 Storage Trends DRAM SRAM Metric1980198519901995200020052010 2010:1980 $/MB50010080.300.010.0050.0003 1,600,000 access (ms)877528108 4329 typical size (MB) 1101601,00020,000160,0001,500,000 1,500,000 Disk Metric1980198519901995200020052010 2010:1980 $/MB19,2002,9003202561007560 320 access (ns)3001503515321.5 200
Carnegie Mellon 44 Saint Louis University CPU Clock Rates 1980199019952000200320052010 2010:1980 CPU8080386Pentium P-III P-4Core 2Core i7 --- Clock rate (MHz) 1 20 150 6003300 2000 2500 2500 Cycle time (ns)1000 50 6 1.6 0.3 0.50 0.4 2500 Cores 1 1 1 1 1 2 4 4 Effective cycle 1000 50 6 1.6 0.3 0.25 0.1 10,000 time (ns) Inflection point in computer history when designers hit the “Power Wall”
Carnegie Mellon 45 Saint Louis University The CPU-Memory Gap Disk DRAM CPU SSD
Carnegie Mellon 46 Saint Louis University Storage Technologies and Memory Hierarchy Storage Technologies and Trends RAM Nonvolatile memory Disk Trends Locality, Cache, and Memory Hierarchy to the Rescue!
Carnegie Mellon 47 Saint Louis University Locality and Cache to the Rescue! The key to bridging this Processor-Memory gap is a fundamental property of computer programs known as… Locality
Carnegie Mellon 48 Saint Louis University Locality Principle of Locality: Programs tend to use data and instructions with the same or neighboring addresses as those they have used recently Temporal locality: Recently referenced items are likely to be referenced again in the near future Spatial locality: Items with nearby addresses tend to be referenced close together in time (will discuss locality in more detail later in semester…)
Carnegie Mellon 49 Saint Louis University Caches Cache: A smaller, faster memory device that acts as a staging area for a subset of the data from a larger, slower device that subset of data frequently exhibits good locality Cache memory can be made very fast using SRAM BUT, fast caches are small Making caches larger quickly reduces speed How to get BOTH size and speed? Cache memory takes advantage of locality … the Memory Hierarchy
Carnegie Mellon 50 Saint Louis University Memory Hierarchy Registers L1 cache (SRAM) Main memory (DRAM) Local secondary storage (local disks) Larger, slower, cheaper per byte Remote secondary storage (tapes, distributed file systems, Web servers) Local disks hold files retrieved from disks on remote network servers Main memory holds disk blocks retrieved from local disks L2 cache (SRAM) L1 cache holds cache lines retrieved from L2 cache CPU registers hold words retrieved from L1 cache L2 cache holds cache lines retrieved from main memory L0: L1: L2: L3: L4: L5: Smaller, faster, more expensive per byte
Carnegie Mellon 51 Saint Louis University Caches Fundamental idea of a memory hierarchy: For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1. Why do memory hierarchies work? Because of locality, programs tend to access the data at level k more often than they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit. Big Idea: The memory hierarchy creates a large pool of storage that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top.
Carnegie Mellon 52 Saint Louis University Intel Core i7 Cache Hierarchy Regs L1 d-cache L1 i-cache L2 unified cache Core 0 Regs L1 d-cache L1 i-cache L2 unified cache Core 3 … L3 unified cache (shared by all cores) Main memory Processor package L1 i-cache and d-cache: 32 KB, 8-way, Access: 4 cycles L2 unified cache: 256 KB, 8-way, Access: 11 cycles L3 unified cache: 8 MB, 16-way, Access: 30-40 cycles Block size: 64 bytes for all caches.
Carnegie Mellon 53 Saint Louis University Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (misses / accesses) = 1 – hit rate Typical numbers (in percentages): 3-10% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor includes time to determine whether the line is in the cache Typical numbers: 1-2 clock cycle for L1 5-20 clock cycles for L2 Miss Penalty Additional time required because of a miss typically 50-200 cycles for main memory (Trend: increasing!)
Carnegie Mellon 54 Saint Louis University Lets think about those numbers Huge difference between a hit and a miss Could be 100x, if just L1 and main memory Would you believe 99% hits is twice as good as 97%? Consider: cache hit time of 1 cycle miss penalty of 100 cycles Average access time: 97% hits: 1 cycle + 0.03 * 100 cycles = 4 cycles 99% hits: 1 cycle + 0.01 * 100 cycles = 2 cycles This is why “miss rate” is used instead of “hit rate”
Carnegie Mellon 55 Saint Louis University Summary The speed gap between processor, memory, and mass storage continues to widen. Memory hierarchies based on caching close the gap by exploiting locality.