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Instructor: Erol Sahin The Memory Hierarchy CENG331: Introduction to Computer Systems 10 th Lecture Acknowledgement: Most of the slides are adapted from.

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Presentation on theme: "Instructor: Erol Sahin The Memory Hierarchy CENG331: Introduction to Computer Systems 10 th Lecture Acknowledgement: Most of the slides are adapted from."— Presentation transcript:

1 Instructor: Erol Sahin The Memory Hierarchy CENG331: Introduction to Computer Systems 10 th Lecture Acknowledgement: Most of the slides are adapted from the ones prepared by R.E. Bryant, D.R. O’Hallaron of Carnegie-Mellon Univ.

2 – 2 – Overview Topics Storage technologies and trends Locality of reference Caching in the memory hierarchy

3 – 3 – Random-Access Memory (RAM) Key features RAM is packaged as a chip. Basic storage unit is a cell (one bit per cell). Multiple RAM chips form a memory. Static RAM (SRAM) Each cell stores bit with a six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to disturbances such as electrical noise. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor and transistor. Value must be refreshed every ms. Sensitive to disturbances. Slower and cheaper than SRAM.

4 – 4 – SRAM Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit. SRAM is more expensive, but faster and significantly less power hungry (especially idle) than DRAM. It is therefore used where either bandwidth or low power, or both, are principal considerations. SRAM is also easier to control (interface to) and generally more truly random access than modern types of DRAM. Due to a more complex internal structure, SRAM is less dense than DRAM and is therefore NOT USED for high- capacity, low-cost applications such as the main memory in personal computers. DRAM

5 – 5 – DRAM DRAM is usually arranged in a square array of one capacitor and transistor per data bit storage cell. The illustrations to the right show a simple example with only 4 by 4 cells Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since real capacitors leak charge, the information eventually fades unless the capacitor charge is refreshed periodically. Because of this refresh requirement, it is a dynamic memory as opposed to SRAM and other static memory. The main memory (the "RAM") in personal computers is Dynamic RAM (DRAM), as is the "RAM" of home game consoles (PlayStation, Xbox 360 and Wii), laptop, notebook and workstation computers. The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are required per bit, compared to six transistors in SRAM. This allows DRAM to reach very high density. Unlike flash memory, it is volatile memory (cf. non- volatile memory), since it loses its data when power is removed. The transistors and capacitors used are extremely small—millions can fit on a single memory chip.

6 – 6 – SRAM vs DRAM Summary Tran.Access per bit timePersist?Sensitive?CostApplications SRAM61XYesNo100xcache memories DRAM160XNoYes1XMain memories, frame buffers

7 – 7 – Conventional DRAM Organization d x w DRAM: dw total bits organized as d supercells of size w bits cols rows internal row buffer 16 x 8 DRAM chip addr data supercell (2,1) 2 bits / 8 bits / memory controller (to CPU)

8 – 8 – Reading DRAM Supercell (2,1) Step 1(a): Row access strobe (RAS) selects row 2. cols rows RAS = internal row buffer 16 x 8 DRAM chip 3 addr data 2/2/ 8/8/ memory controller Step 1(b): Row 2 copied from DRAM array to row buffer.

9 – 9 – Reading DRAM Supercell (2,1) Step 2(a): Column access strobe (CAS) selects column 1. internal buffer cols rows internal row buffer 16 x 8 DRAM chip CAS = 1 addr data 2/2/ 8/8/ memory controller Step 2(b): Supercell (2,1) copied from buffer to data lines, and eventually back to the CPU. supercell (2,1) supercell (2,1) To CPU

10 – 10 – Memory Modules : supercell (i,j) 64 MB memory module consisting of eight 8Mx8 DRAMs addr (row = i, col = j) Memory controller DRAM 7 DRAM bit doubleword at main memory address A bits 0-7 bits 8-15 bits bits bits bits bits bits bit doubleword bit doubleword at main memory address A

11 – 11 – Enhanced DRAMs All enhanced DRAMs are built around the conventional DRAM core. Fast page mode DRAM (FPM DRAM) Access contents of row with [RAS, CAS, CAS, CAS, CAS] instead of [(RAS,CAS), (RAS,CAS), (RAS,CAS), (RAS,CAS)]. Extended data out DRAM (EDO DRAM) Enhanced FPM DRAM with more closely spaced CAS signals. Synchronous DRAM (SDRAM) Driven with rising clock edge instead of asynchronous control signals. Double data-rate synchronous DRAM (DDR SDRAM) Enhancement of SDRAM that uses both clock edges as control signals. Video RAM (VRAM) Like FPM DRAM, but output is produced by shifting row buffer Dual ported (allows concurrent reads and writes)

12 – 12 – Nonvolatile Memories DRAM and SRAM are volatile memories Lose information if powered off. Nonvolatile memories retain value even if powered off. Generic name is read-only memory (ROM). Misleading because some ROMs can be read and modified. Types of ROMs Programmable ROM (PROM) Erasable programmable ROM (EPROM) Electrically erase PROM (EEPROM) Flash memoryFirmware Program stored in a ROM Boot time code, BIOS (basic input/ouput system) graphics cards, disk controllers.

13 – 13 – Traditional Bus Structure Connecting CPU and Memory A bus is a collection of parallel wires that carry address, data, and control signals. Buses are typically shared by multiple devices. Main memory I/O bridge Bus interface ALU Register file CPU chip System busMemory bus

14 – 14 – Memory Read Transaction (1) CPU places address A on the memory bus. ALU Register file Bus interface A 0 A x Main memory I/O bridge %eax Load operation: movl A, %eax

15 – 15 – Memory Read Transaction (2) Main memory reads A from the memory bus, retrieves word x, and places it on the bus. ALU Register file Bus interface x 0 A x Main memory %eax I/O bridge Load operation: movl A, %eax

16 – 16 – Memory Read Transaction (3) CPU read word x from the bus and copies it into register %eax. x ALU Register file Bus interface x Main memory 0 A %eax I/O bridge Load operation: movl A, %eax

17 – 17 – Memory Write Transaction (1) CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. CPU places address A on bus. Main memory reads it and waits for the corresponding data word to arrive. y ALU Register file Bus interface A Main memory 0 A %eax I/O bridge Store operation: movl %eax, A

18 – 18 – Memory Write Transaction (2) CPU places data word y on the bus. CPU places data word y on the bus. y ALU Register file Bus interface y Main memory 0 A %eax I/O bridge Store operation: movl %eax, A

19 – 19 – Memory Write Transaction (3) Main memory reads data word y from the bus and stores it at address A. Main memory reads data word y from the bus and stores it at address A. y ALU register file bus interface y main memory 0 A %eax I/O bridge Store operation: movl %eax, A

20 – 20 – What’s Inside A Disk Drive? Spindle Arm Actuator Platters Electronics (including a processor and memory!) SCSI connector Image courtesy of Seagate Technology

21 – 21 – Disk Geometry Disks consist of platters, each with two surfaces. Each surface consists of concentric rings called tracks. Each track consists of sectors separated by gaps. Spindle Surface Tracks Track k Sectors Gaps

22 – 22 – Disk Geometry (Muliple-Platter View) Aligned tracks form a cylinder. Aligned tracks form a cylinder. Surface 0 Surface 1 Surface 2 Surface 3 Surface 4 Surface 5 Cylinder k Spindle Platter 0 Platter 1 Platter 2

23 – 23 – Disk Capacity Capacity: maximum number of bits that can be stored. Vendors express capacity in units of gigabytes (GB), where 1 GB = 10^9 Bytes (Lawsuit pending! Claims deceptive advertising). Capacity is determined by these technology factors: Recording density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track. Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment. Areal density (bits/in2): product of recording and track density. Modern disks partition tracks into disjoint subsets called recording zones Each track in a zone has the same number of sectors, determined by the circumference of innermost track. Each zone has a different number of sectors/track

24 – 24 – Computing Disk Capacity Capacity = (# bytes/sector) x (avg. # sectors/track) x (# tracks/surface) x (# surfaces/platter) x (# tracks/surface) x (# surfaces/platter) x (# platters/disk) (# platters/disk)Example: 512 bytes/sector 300 sectors/track (on average) 20,000 tracks/surface 2 surfaces/platter 5 platters/disk Capacity = 512 x 300 x x 2 x 5 = 30,720,000,000 = 30,720,000,000 = GB = GB

25 – 25 – Disk Operation (Single-Platter View) The disk surface spins at a fixed rotational rate By moving radially, the arm can position the read/write head over any track. The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. spindle

26 – 26 – Disk Operation (Multi-Platter View) Arm Read/write heads move in unison from cylinder to cylinder Spindle

27 – 27 – Tracks divided into sectors Disk Structure - top view of single platter Surface organized into tracks

28 – 28 – Disk Access Head in position above a track

29 – 29 – Disk Access Rotation is counter-clockwise

30 – 30 – Disk Access – Read About to read blue sector

31 – 31 – Disk Access – Read After BLUE read After reading blue sector

32 – 32 – Disk Access – Read After BLUE read Red request scheduled next

33 – 33 – Disk Access – Seek After BLUE read Seek for RED Seek to red’s track

34 – 34 – Disk Access – Rotational Latency After BLUE read Seek for REDRotational latency Wait for red sector to rotate around

35 – 35 – Disk Access – Read After BLUE read Seek for REDRotational latencyAfter RED read Complete read of red

36 – 36 – Disk Access – Service Time Components After BLUE read Seek for REDRotational latencyAfter RED read Data transferSeekRotational latency Data transfer

37 – 37 – Disk Access Time Average time to access some target sector approximated by : Taccess = Tavg seek + Tavg rotation + Tavg transfer Seek time (Tavg seek) Time to position heads over cylinder containing target sector. Typical Tavg seek is 3—9 ms Rotational latency (Tavg rotation) Time waiting for first bit of target sector to pass under r/w head. Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min Typical Tavg rotation = 7200 RPMs Transfer time (Tavg transfer) Time to read the bits in the target sector. Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

38 – 38 – Disk Access Time Example Given: Rotational rate = 7,200 RPM Average seek time = 9 ms. Avg # sectors/track = 400.Derived: Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms Taccess = 9 ms + 4 ms ms Important points: Access time dominated by seek time and rotational latency. First bit in a sector is the most expensive, the rest are free. SRAM access time is about 4 ns/doubleword, DRAM about 60 ns Disk is about 40,000 times slower than SRAM, 2,500 times slower then DRAM.

39 – 39 – Logical Disk Blocks Modern disks present a simpler abstract view of the complex sector geometry: The set of available sectors is modeled as a sequence of b-sized logical blocks (0, 1, 2,...) Mapping between logical blocks and actual (physical) sectors Maintained by hardware/firmware device called disk controller. Converts requests for logical blocks into (surface,track,sector) triples. Allows controller to set aside spare cylinders for each zone. Accounts for the difference in “formatted capacity” and “maximum capacity”.

40 – 40 – I/O Bus Main memory I/O bridge Bus interface ALU Register file CPU chip System busMemory bus Disk controller Graphics adapter USB controller MouseKeyboardMonitor Disk I/O bus Expansion slots for other devices such as network adapters.

41 – 41 – Reading a Disk Sector (1) Main memory ALU Register file CPU chip Disk controller Graphics adapter USB controller mouse keyboard Monitor Disk I/O bus Bus interface CPU initiates a disk read by writing a command, logical block number, and destination memory address to a port (address) associated with disk controller.

42 – 42 – Reading a Disk Sector (2) Main memory ALU Register file CPU chip Disk controller Graphics adapter USB controller MouseKeyboardMonitor Disk I/O bus Bus interface Disk controller reads the sector and performs a direct memory access (DMA) transfer into main memory.

43 – 43 – Reading a Disk Sector (3) Main memory ALU Register file CPU chip Disk controller Graphics adapter USB controller MouseKeyboardMonitor Disk I/O bus Bus interface When the DMA transfer completes, the disk controller notifies the CPU with an interrupt (i.e., asserts a special “interrupt” pin on the CPU)

44 – 44 – Solid State Disks (SSDs) Pages: 512KB to 4KB, Blocks: 32 to 128 pages Data read/written in units of pages. Page can be written only after its block has been erased A block wears out after 100,000 repeated writes. Flash translation layer I/O bus Page 0Page 1 Page P-1 … Block 0 … Page 0Page 1 Page P-1 … Block B-1 Flash memory Solid State Disk (SSD) Requests to read and write logical disk blocks

45 – 45 – SSD Performance Characteristics Why are random writes so slow? Erasing a block is slow (around 1 ms) Write to a page triggers a copy of all useful pages in the block Find an used block (new block) and erase it Write the page into the new block Copy other pages from old block to the new block Sequential read tput250 MB/sSequential write tput170 MB/s Random read tput140 MB/sRandom write tput14 MB/s Rand read access30 usRandom write access300 us

46 – 46 – SSD Tradeoffsvs Rotating Disks Advantages No moving parts  faster, less power, more ruggedDisadvantages Have the potential to wear out Mitigated by “wear leveling logic” in flash translation layer E.g. Intel X25 guarantees 1 petabyte (10^15 bytes) of random writes before they wear out In 2010, about 100 times more expensive per byteApplications MP3 players, smart phones, laptops Beginning to appear in desktops and servers

47 – 47 – Metric :1980 $/MB8, ,000 access (ns) typical size (MB) ,0008,000125,000 Storage Trends DRAM SRAM Metric :1980 $/MB ,600,000 access (ms) typical size (MB) ,00020,000160,0001,500,0001,500,000 Disk Metric :1980 $/MB19,2002, access (ns)

48 – 48 – CPU Clock Rates :1980 CPU PentiumP-IIIP-4Core 2Core i7--- Clock rate (MHz) Cycle time (ns) Cores Effective cycle ,000 time (ns) Inflection point in computer history when designers hit the “Power Wall”

49 – 49 – The CPU-Memory Gap Disk DRAM CPU SSD

50 – 50 – Locality to the Rescue! The key to bridging this CPU-Memory gap is a fundamental property of computer programs known as locality

51 – 51 – Locality Principle of Locality: Programs tend to use data and instructions with addresses near or equal to those they have used recently Temporal locality: Recently referenced items are likely to be referenced again in the near future Spatial locality: Items with nearby addresses tend to be referenced close together in time

52 – 52 – Locality Example Data references Reference array elements in succession (stride-1 reference pattern). Reference variable sum each iteration. Instruction references Reference instructions in sequence. Cycle through loop repeatedly. sum = 0; for (i = 0; i < n; i++) sum += a[i]; return sum; Spatial locality Temporal locality Spatial locality Temporal locality

53 – 53 – Qualitative Estimates of Locality Claim: Being able to look at code and get a qualitative sense of its locality is a key skill for a professional programmer. Question: Does this function have good locality with respect to array a ? int sum_array_rows(int a[M][N]) { int i, j, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) sum += a[i][j]; return sum; }

54 – 54 – Locality Example Question: Does this function have good locality with respect to array a ? int sum_array_cols(int a[M][N]) { int i, j, sum = 0; for (j = 0; j < N; j++) for (i = 0; i < M; i++) sum += a[i][j]; return sum; }

55 – 55 – Locality Example Question: Can you permute the loops so that the function scans the 3-d array a with a stride-1 reference pattern (and thus has good spatial locality)? int sum_array_3d(int a[M][N][N]) { int i, j, k, sum = 0; for (i = 0; i < M; i++) for (j = 0; j < N; j++) for (k = 0; k < N; k++) sum += a[k][i][j]; return sum; }

56 – 56 – Memory Hierarchies Some fundamental and enduring properties of hardware and software: Fast storage technologies cost more per byte, have less capacity, and require more power (heat!). The gap between CPU and main memory speed is widening. Well-written programs tend to exhibit good locality. These fundamental properties complement each other beautifully. They suggest an approach for organizing memory and storage systems known as a memory hierarchy.

57 – 57 – An Example Memory Hierarchy Registers L1 cache (SRAM) Main memory (DRAM) Local secondary storage (local disks) Larger, slower, cheaper per byte Remote secondary storage (tapes, distributed file systems, Web servers) Local disks hold files retrieved from disks on remote network servers Main memory holds disk blocks retrieved from local disks L2 cache (SRAM) L1 cache holds cache lines retrieved from L2 cache CPU registers hold words retrieved from L1 cache L2 cache holds cache lines retrieved from main memory L0: L1: L2: L3: L4: L5: Smaller, faster, costlier per byte

58 – 58 – Caches Cache: A smaller, faster storage device that acts as a staging area for a subset of the data in a larger, slower device. Fundamental idea of a memory hierarchy: For each k, the faster, smaller device at level k serves as a cache for the larger, slower device at level k+1. Why do memory hierarchies work? Because of locality, programs tend to access the data at level k more often than they access the data at level k+1. Thus, the storage at level k+1 can be slower, and thus larger and cheaper per bit. Big Idea: The memory hierarchy creates a large pool of storage that costs as much as the cheap storage near the bottom, but that serves data to programs at the rate of the fast storage near the top.

59 – 59 – General Cache Concepts Cache Memory Larger, slower, cheaper memory viewed as partitioned into “blocks” Data is copied in block-sized transfer units Smaller, faster, more expensive memory caches a subset of the blocks

60 – 60 – General Cache Concepts: Hit Cache Memory Data in block b is needed Request: Block b is in cache: Hit!

61 – 61 – General Cache Concepts: Miss Cache Memory Data in block b is needed Request: 12 Block b is not in cache: Miss! Block b is fetched from memory Request: Block b is stored in cache Placement policy: determines where b goes Replacement policy: determines which block gets evicted (victim)

62 – 62 – General Caching Concepts: Types of Cache Misses Cold (compulsory) miss Cold misses occur because the cache is empty. Conflict miss Most caches limit blocks at level k+1 to a small subset (sometimes a singleton) of the block positions at level k. E.g. Block i at level k+1 must be placed in block (i mod 4) at level k. Conflict misses occur when the level k cache is large enough, but multiple data objects all map to the same level k block. E.g. Referencing blocks 0, 8, 0, 8, 0, 8,... would miss every time. Capacity miss Occurs when the set of active cache blocks (working set) is larger than the cache.

63 – 63 – Examples of Caching in the Hierarchy Hardware0On-Chip TLBAddress translationsTLB Web browser10,000,000Local diskWeb pagesBrowser cache Web cache Network buffer cache Buffer cache Virtual Memory L2 cache L1 cache Registers Cache Type Web pages Parts of files 4-KB page 64-bytes block 4-8 bytes words What is Cached? Web proxy server 1,000,000,000Remote server disks OS100Main memory Hardware1On-Chip L1 Hardware10On/Off-Chip L2 AFS/NFS client10,000,000Local disk Hardware + OS100Main memory Compiler0 CPU core Managed ByLatency (cycles)Where is it Cached? Disk cacheDisk sectorsDisk controller100,000Disk firmware

64 – 64 – Summary The speed gap between CPU, memory and mass storage continues to widen. Well-written programs exhibit a property called locality. Memory hierarchies based on caching close the gap by exploiting locality.

65 Cache Memories CENG331: Introduction to Computer Systems 10 th Lecture. Instructor: Erol Sahin

66 – 66 – Today Cache memory organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality

67 – 67 – Cache Memories Cache memories are small, fast SRAM-based memories managed automatically in hardware. Hold frequently accessed blocks of main memory CPU looks first for data in caches (e.g., L1, L2, and L3), then in main memory. Typical system structure: Main memory I/O bridge Bus interface ALU Register file CPU chip System busMemory bus Cache memories

68 – 68 – General Cache Organization (S, E, B) E = 2 e lines per set S = 2 s sets set line 012 B-1 tag v B = 2 b bytes per cache block (the data) Cache size: C = S x E x B data bytes valid bit

69 – 69 – Cache Read E = 2 e lines per set S = 2 s sets 012 B-1tag v valid bit B = 2 b bytes per cache block (the data) t bitss bits b bits Address of word: tag set index block offset data begins at this offset Locate set Check if any line in set has matching tag Yes + line valid: hit Locate data starting at offset

70 – 70 – Example: Direct Mapped Cache (E = 1) S = 2 s sets Direct mapped: One line per set Assume: cache block size 8 bytes t bits0… Address of int: 0127tagv v v v3654 find set

71 – 71 – Example: Direct Mapped Cache (E = 1) Direct mapped: One line per set Assume: cache block size 8 bytes t bits0… Address of int: 0127tagv3654 match: assume yes = hitvalid? + block offset tag

72 – 72 – Example: Direct Mapped Cache (E = 1) Direct mapped: One line per set Assume: cache block size 8 bytes t bits0… Address of int: 0127tagv3654 match: assume yes = hitvalid? + int (4 Bytes) is here block offset No match: old line is evicted and replaced

73 – 73 – Direct-Mapped Cache Simulation M=16 byte addresses, B=2 bytes/block, S=4 sets, E=1 Blocks/set Address trace (reads, one byte per read): 0[ ], 1[ ], 7[ ], 8[ ], 0[ ] x t=1s=2b=1 xxx 0?? vTagBlock miss 10M[0-1] hit miss 10M[6-7] miss 11M[8-9] miss 10M[0-1] Set 0 Set 1 Set 2 Set 3

74 – 74 – A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; } 32 B = 4 doubles assume: cold (empty) cache, a[0][0] goes here int sum_array_cols(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; } blackboard Ignore the variables sum, i, j

75 – 75 – E-way Set Associative Cache (Here: E = 2) E = 2: Two lines per set Assume: cache block size 8 bytes t bits0… Address of short int: 0127tagv v v v v v v v3654 find set

76 – 76 – E-way Set Associative Cache (Here: E = 2) E = 2: Two lines per set Assume: cache block size 8 bytes t bits0… Address of short int: 0127tagv v3654 compare both valid? + match: yes = hit block offset tag

77 – 77 – E-way Set Associative Cache (Here: E = 2) E = 2: Two lines per set Assume: cache block size 8 bytes t bits0… Address of short int: 0127tagv v3654 compare both valid? +match: yes = hit block offset short int (2 Bytes) is here No match: One line in set is selected for eviction and replacement Replacement policies: random, least recently used (LRU), …

78 – 78 – 2-Way Set Associative Cache Simulation M=16 byte addresses, B=2 bytes/block, S=2 sets, E=2 blocks/set Address trace (reads, one byte per read): 0[ ], 1[ ], 7[ ], 8[ ], 0[ ] xx t=2s=1b=1 xx 0?? vTagBlock miss 100M[0-1] hit miss 101M[6-7] miss 110M[8-9] hit Set 0 Set 1

79 – 79 – A Higher Level Example int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (i = 0; i < 16; i++) for (j = 0; j < 16; j++) sum += a[i][j]; return sum; } 32 B = 4 doubles assume: cold (empty) cache, a[0][0] goes here int sum_array_rows(double a[16][16]) { int i, j; double sum = 0; for (j = 0; i < 16; i++) for (i = 0; j < 16; j++) sum += a[i][j]; return sum; } blackboard Ignore the variables sum, i, j

80 – 80 – What about writes? Multiple copies of data exist: L1, L2, Main Memory, Disk What to do on a write-hit? Write-through (write immediately to memory) Write-back (defer write to memory until replacement of line) Need a dirty bit (line different from memory or not) What to do on a write-miss? Write-allocate (load into cache, update line in cache) Good if more writes to the location follow No-write-allocate (writes immediately to memory)Typical Write-through + No-write-allocate Write-back + Write-allocate

81 – 81 – Intel Core i7 Cache Hierarchy Regs L1 d-cache L1 i-cache L2 unified cache Core 0 Regs L1 d-cache L1 i-cache L2 unified cache Core 3 … L3 unified cache (shared by all cores) Main memory Processor package L1 i-cache and d-cache: 32 KB, 8-way, Access: 4 cycles L2 unified cache: 256 KB, 8-way, Access: 11 cycles L3 unified cache: 8 MB, 16-way, Access: cycles Block size: 64 bytes for all caches.

82 – 82 – Cache Performance Metrics Miss Rate Fraction of memory references not found in cache (misses / accesses) = 1 – hit rate Typical numbers (in percentages): 3-10% for L1 can be quite small (e.g., < 1%) for L2, depending on size, etc. Hit Time Time to deliver a line in the cache to the processor includes time to determine whether the line is in the cache Typical numbers: 1-2 clock cycle for L clock cycles for L2 Miss Penalty Additional time required because of a miss typically cycles for main memory (Trend: increasing!)

83 – 83 – Lets think about those numbers Huge difference between a hit and a miss Could be 100x, if just L1 and main memory Would you believe 99% hits is twice as good as 97%? Consider: cache hit time of 1 cycle miss penalty of 100 cycles Average access time: 97% hits: 1 cycle * 100 cycles = 4 cycles 99% hits: 1 cycle * 100 cycles = 2 cycles This is why “miss rate” is used instead of “hit rate”

84 – 84 – Writing Cache Friendly Code Make the common case go fast Focus on the inner loops of the core functions Minimize the misses in the inner loops Repeated references to variables are good (temporal locality) Stride-1 reference patterns are good (spatial locality) Key idea: Our qualitative notion of locality is quantified through our understanding of cache memories.

85 – 85 – Today Cache organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality

86 – 86 – The Memory Mountain Read throughput (read bandwidth) Number of bytes read from memory per second (MB/s) Memory mountain: Measured read throughput as a function of spatial and temporal locality. Compact way to characterize memory system performance.

87 – 87 – Memory Mountain Test Function /* The test function */ void test(int elems, int stride) { int i, result = 0; volatile int sink; for (i = 0; i < elems; i += stride) result += data[i]; sink = result; /* So compiler doesn't optimize away the loop */ } /* Run test(elems, stride) and return read throughput (MB/s) */ double run(int size, int stride, double Mhz) { double cycles; int elems = size / sizeof(int); test(elems, stride); /* warm up the cache */ cycles = fcyc2(test, elems, stride, 0); /* call test(elems,stride) */ return (size / stride) / (cycles / Mhz); /* convert cycles to MB/s */ }

88 – 88 – The Memory Mountain Intel Core i7 32 KB L1 i-cache 32 KB L1 d-cache 256 KB unified L2 cache 8M unified L3 cache All caches on-chip

89 – 89 – The Memory Mountain Intel Core i7 32 KB L1 i-cache 32 KB L1 d-cache 256 KB unified L2 cache 8M unified L3 cache All caches on-chip Slopes of spatial locality

90 – 90 – The Memory Mountain Intel Core i7 32 KB L1 i-cache 32 KB L1 d-cache 256 KB unified L2 cache 8M unified L3 cache All caches on-chip Slopes of spatial locality Ridges of Temporal locality

91 – 91 – Today Cache organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality

92 – 92 – Miss Rate Analysis for Matrix Multiply Assume: Line size = 32B (big enough for four 64-bit words) Matrix dimension (N) is very large Approximate 1/N as 0.0 Cache is not even big enough to hold multiple rows Analysis Method: Look at access pattern of inner loop A k i B k j C i j

93 – 93 – Matrix Multiplication Example Description: Multiply N x N matrices O(N 3 ) total operations N reads per source element N values summed per destination but may be able to hold in register /* ijk */ for (i=0; i

94 – 94 – Layout of C Arrays in Memory (review) C arrays allocated in row-major order each row in contiguous memory locations Stepping through columns in one row: for (i = 0; i < N; i++) sum += a[0][i]; accesses successive elements if block size (B) > 4 bytes, exploit spatial locality compulsory miss rate = 4 bytes / B Stepping through rows in one column: for (i = 0; i < n; i++) sum += a[i][0]; accesses distant elements no spatial locality! compulsory miss rate = 1 (i.e. 100%)

95 – 95 – Matrix Multiplication (ijk) /* ijk */ for (i=0; i

96 – 96 – Matrix Multiplication (jik) /* jik */ for (j=0; j

97 – 97 – Matrix Multiplication (kij) /* kij */ for (k=0; k

98 – 98 – Matrix Multiplication (ikj) /* ikj */ for (i=0; i

99 – 99 – Matrix Multiplication (jki) /* jki */ for (j=0; j

100 – 100 – Matrix Multiplication (kji) /* kji */ for (k=0; k

101 – 101 – Summary of Matrix Multiplication ijk (& jik): 2 loads, 0 stores misses/iter = 1.25 kij (& ikj): 2 loads, 1 store misses/iter = 0.5 jki (& kji): 2 loads, 1 store misses/iter = 2.0 for (i=0; i

102 – 102 – Core i7 Matrix Multiply Performance jki / kji ijk / jik kij / ikj

103 – 103 – Today Cache organization and operation Performance impact of caches The memory mountain Rearranging loops to improve spatial locality Using blocking to improve temporal locality

104 – 104 – Example: Matrix Multiplication ab i j * c = c = (double *) calloc(sizeof(double), n*n); /* Multiply n x n matrices a and b */ void mmm(double *a, double *b, double *c, int n) { int i, j, k; for (i = 0; i < n; i++) for (j = 0; j < n; j++) for (k = 0; k < n; k++) c[i*n+j] += a[i*n + k]*b[k*n + j]; }

105 – 105 – Cache Miss Analysis Assume: Matrix elements are doubles Cache block = 8 doubles Cache size C << n (much smaller than n) First iteration: n/8 + n = 9n/8 misses Afterwards in cache: (schematic) * = n * = 8 wide

106 – 106 – Cache Miss Analysis Assume: Matrix elements are doubles Cache block = 8 doubles Cache size C << n (much smaller than n) Second iteration: Again: n/8 + n = 9n/8 misses Total misses: 9n/8 * n 2 = (9/8) * n 3 n * = 8 wide

107 – 107 – Blocked Matrix Multiplication c = (double *) calloc(sizeof(double), n*n); /* Multiply n x n matrices a and b */ void mmm(double *a, double *b, double *c, int n) { int i, j, k; for (i = 0; i < n; i+=B) for (j = 0; j < n; j+=B) for (k = 0; k < n; k+=B) /* B x B mini matrix multiplications */ for (i1 = i; i1 < i+B; i++) for (j1 = j; j1 < j+B; j++) for (k1 = k; k1 < k+B; k++) c[i1*n+j1] += a[i1*n + k1]*b[k1*n + j1]; } ab i1 j1 * c = c + Block size B x B

108 – 108 – Cache Miss Analysis Assume: Cache block = 8 doubles Cache size C << n (much smaller than n) Three blocks fit into cache: 3B 2 < C First (block) iteration: B 2 /8 misses for each block 2n/B * B 2 /8 = nB/4 (omitting matrix c) Afterwards in cache (schematic) * = * = Block size B x B n/B blocks

109 – 109 – Cache Miss Analysis Assume: Cache block = 8 doubles Cache size C << n (much smaller than n) Three blocks fit into cache: 3B 2 < C Second (block) iteration: Same as first iteration 2n/B * B 2 /8 = nB/4 Total misses: nB/4 * (n/B) 2 = n 3 /(4B) * = Block size B x B n/B blocks

110 – 110 – Summary No blocking: (9/8) * n 3 Blocking: 1/(4B) * n 3 Suggest largest possible block size B, but limit 3B 2 < C! Reason for dramatic difference: Matrix multiplication has inherent temporal locality: Input data: 3n 2, computation 2n 3 Every array elements used O(n) times! But program has to be written properly

111 – 111 – Concluding Observations Programmer can optimize for cache performance How data structures are organized How data are accessed Nested loop structure Blocking is a general technique All systems favor “cache friendly code” Getting absolute optimum performance is very platform specific Cache sizes, line sizes, associativities, etc. Can get most of the advantage with generic code Keep working set reasonably small (temporal locality) Use small strides (spatial locality)


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