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**Topic 4 Field-Effect Transistors**

ECE 271 Electronic Circuits I Topic 4 Field-Effect Transistors NJIT ECE271 Dr. Serhiy Levkov

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**Chapter Goals Describe structure and operation of MOSFETs.**

Define FET characteristics in operation regions of cutoff, triode and saturation. Develop mathematical models for i-v characteristics of MOSFETs. Introduce graphical representations for output and transfer characteristic descriptions of electron devices. Define and contrast characteristics of enhancement-mode and depletion-mode FETs. Define symbols to represent FETs in circuit schematics. Investigate circuits that bias transistors into different operating regions. Explore FET modeling in SPICE. NJIT ECE271 Dr. Serhiy Levkov

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Intro (1) Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: NJIT ECE271 Dr. Serhiy Levkov

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Intro (1) Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) NJIT ECE271 Dr. Serhiy Levkov

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Intro (1) Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) NJIT ECE271 Dr. Serhiy Levkov

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Intro (1) Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor). NJIT ECE271 Dr. Serhiy Levkov

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Intro (1) Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) There are two basic types of solid state transistors: BJT (bipolar junction transistor) and FET (field effect transistor). FET: electric field is used to control the shape and the conductivity of the channel of one type charge carrier (p or n) in semiconductor device. They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT). NJIT ECE271 Dr. Serhiy Levkov

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Intro (1) Solid state transistor is the main building block of microelectronics. It performs two major functions used in electronic devices: - amplifications (in analog) - switching (in digital) There are two basic types of solid state transistors BJT (bipolar junction transistor) and FET (field effect transistor). FET: electric filed is used to control the shape and hence the conductivity of the channel of one type charge carrier (p or n) in semiconductor device. They are also called unipolar to contrast their single-carrier-type operation with the dual-carrier-type operation of bipolar (junction) transistors (BJT). FET can be of two major types MOSFET (metal oxide semiconductor field effect transistor (mostly used)), and JFET (junction field effect transistor). NJIT ECE271 Dr. Serhiy Levkov

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Intro (2) Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later. Today, the CMOS technology based on MOSFET is the dominant technology in electronics. NJIT ECE271 Dr. Serhiy Levkov

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Intro (2) Metal Oxide Semiconductor Field Effect device was first solid state device conceived (Lilienfield, 1928), however it took very long to develop a successful commercial application of such devices. The first successful device was fabricated in 1950, however the reliable commercial fabrication did not start until decade later. Today, the CMOS technology based on MOSFET is the dominant technology in electronics. BJT devices were first introduced in 1948 and quickly became commercially available. The first IC with logic gates and operational amplifiers that appeared in early 1960s, were based on BJT technology. They are still widely used, particularly in applications requiring high speed and high precision. BJT device is based on pn-junction structure, while MOSFET is utilizing the MOS capacitor structure. NJIT ECE271 Dr. Serhiy Levkov

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**Metal Oxide Semiconductor Field-Effect Transistors (MOSFET)**

NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Second electrode (Substrate, Body): n- or p-type semiconductor. NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Second electrode (Substrate, Body): n- or p-type semiconductor. The semiconductor body has limited supply of holes and electrons, and substantial resistivity. NJIT ECE271 Dr. Serhiy Levkov

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**MOS Capacitor Structure**

Metal Oxide Semiconductor capacitor is the core structure of the a Metal Oxide Semiconductor Field Effect Transistor. Consists of two electrodes and insulator in between. First electrode (Gate): low-resistivity material such as metal or polycrystalline silicon. Dielectric - Silicon dioxide: stable high-quality electrical insulator between gate and substrate. Second electrode (Substrate, Body): n- or p-type semiconductor. The semiconductor body has limited supply of holes and electrons, and substantial resistivity. The concentration of carriers being dependant on voltage, the capacitance of this structure therefore is a nonlinear function of voltage applied. NJIT ECE271 Dr. Serhiy Levkov

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**Substrate Conditions for Different Biases**

We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by VTN ( V) the threshold voltage, at which the electron inversion layer is just starting to form. Accumulation : VG<<VTN The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) NJIT ECE271 Dr. Serhiy Levkov

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**Substrate Conditions for Different Biases**

We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by VTN ( V) the threshold voltage, at which the electron inversion layer is just starting to form. Accumulation : VG<<VTN , VG<0 The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) Depletion: 0<VG<VTN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms NJIT ECE271 Dr. Serhiy Levkov

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**Substrate Conditions for Different Biases**

We consider the conditions of the semiconductor region (p-type) below the gate electrode under three different voltage bias: accumulation, depletion, inversion. Those conditions are determined by VTN ( V) the threshold voltage, at which the electron inversion layer is just starting to form. Accumulation : VG<<VTN The majority carriers (holes) accumulate in a very thin layer below the negative gate (like in capacitor) Depletion: 0<VG<VTN The small positive charge of the gate wipe out the holes from the layer below (depletes free carriers) creative a negative charge of ionized atoms Inversion: VG>VTN The larger positive charge of the gate attracts electrons whose concentration in the very thin layer exceeds that of holes – inversion of p-type into n-type. NJIT ECE271 Dr. Serhiy Levkov

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**Low-frequency C-V Characteristics for MOS Capacitor on P-type Substrate**

MOS capacitance is non-linear function of voltage. Total capacitance in any region is dictated by the separation between capacitor plates. Total capacitance can be modeled as series combination of fixed oxide capacitance and voltage-dependent depletion layer capacitance. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) Drain(D) NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) Drain(D), Source(S) NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) Drain(D), Source(S) Body(B) NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) Drain(D), Source(S) Body(B). Source and drain regions form pn junctions with substrate. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) Drain(D), Source(S) Body(B). Source and drain regions form pn junctions with substrate. vSB,= vS – vB , vDS = vD - vS and vGS = vG - vS are typically nonnegative during normal operation. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Structure**

A N-MOSFET is formed by adding two heavily doped n-type (n+ , about one of 100 of silicon atoms is replaced with donor), regions to the MOS capacitor. The resulting diffusions provide a supply of electrons that can rapidly form the inversion layer and easily move under the gate, and also make terminals to apply a voltage and create a current in the channel region. 4 device terminals: Gate(G) Drain(D), Source(S) Body(B). Source and drain regions form pn junctions with substrate. vSB,= vS – vB , vDS = vD - vS and vGS = vG - vS are always positive during normal operation. vB <= vD and vB <= vS , to keep pn junctions reverse biased. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor and Variable Resistor**

A transistor is a three (or four) terminal device, in which one terminal controls the voltage or current between other two terminals In certain way it is similar to a variable resistor, in which the movement of the middle terminal controls the voltage. + + - - NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Qualitative Behavior @ vDS =0**

VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Qualitative Behavior @ vDS =0**

VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. VGS<VTN (VGS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Qualitative Behavior @ vDS =0**

VGS<<VTN (VGS <0): Two back to back reverse biased pn junctions btw S and D. Only small leakage current flows. VGS<VTN (VGS >0): Depletion region formed under gate merges with source and drain depletion regions. No current flows between source and drain. VGS>VTN: Channel is formed between source and drain by electrons in inversion layer. If VDS>0, finite iD flows from drain to source. iB=0 and iG=0. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Qualitative Behavior @ vDS =0**

Since the induced inversion layer is formed by electrons, it’s called N-channel MOSFET. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Triode Region**

Applying a small vDS creates a flow of electrons in the induced inversion layer between source and drain - current iD (iD = iS , since iB=0 and iG=0). for where Kn= Kn’W/L – the gain factor Kn’=mnCox’’ (A/V2) Cox’’=ox/Tox ox= oxide permittivity (F/cm) Tox = oxide thickness (cm) This is the triode region (linear region, ohmic mode). MOSFET operates like a resistor, controlled by the gate voltage relative to both the source and drain voltages. NJIT ECE271 Dr. Serhiy Levkov

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**N-MOS Transistor: Triode Region (derivation of the source-drain current)**

Since currents iB and iG both are zero, and there is no path for drain current to escape: iS = iD. To find it, we consider the transport of the charge. The linear density of the electron charge at any point in the channel is: The voltage vox is the function of position x in the channel: For inversion layer to exist, should be vox > VTN , so Q’ = 0 until vox > VTN . At the source, vox = vGS and it decrease to vox = vGS - vDS at the drain. The electron drift current is : , where Combining everything: and integrating: , we get NJIT ECE271 Dr. Serhiy Levkov

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**Triode (a bit of history)**

A triode is an electronic amplification device having three active electrodes. most commonly it’s a vacuum tube with three elements: the filament (cathode), the grid (controlling element), and the plate or anode. The triode vacuum tube was the first electronic amplification device. It’s iv-characteristics was quite linear. NJIT ECE271 Dr. Serhiy Levkov

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**N-MOSFET: Triode Region Characteristics**

The expression for iD is quadratic in vDS NJIT ECE271 Dr. Serhiy Levkov

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**N-MOSFET: Triode Region Characteristics**

The expression for iD is quadratic in vDS with max reached at vDS = vGS - vTN = vOV vDS NJIT ECE271 Dr. Serhiy Levkov

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**N-MOSFET: Triode Region Characteristics**

The expression for iD is quadratic in vDS with max reached at vDS = vGS - vTN = vOV For small vDS << vGS - vTN , the characteristics iD vs. vDS appear to be linear (triode region, linear) vDS NJIT ECE271 Dr. Serhiy Levkov

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**N-MOSFET: Triode Region Characteristics**

The expression for iD is quadratic in vDS with max reached at vDS = vGS - vTN = vOV For small vDS << vGS - vTN , the characteristics iD vs. vDS appear to be linear (triode region, linear) Under this condition, MOSFET behaves like a gate-source voltage-controlled resistor between source and drain, NJIT ECE271 Dr. Serhiy Levkov

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**N-MOSFET: Triode Region Characteristics**

The expression for iD is quadratic in vDS with max reached at vDS = vGS - vTN = vOV For small vDS << vGS - vTN , the characteristics iD vs. vDS appear to be linear (triode region, linear) Under this condition, MOSFET behaves like a gate-source voltage-controlled resistor between source and drain, where on-resistance: NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: NJIT ECE271 Dr. Serhiy Levkov

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**MOSFET as Voltage-Controlled Resistor**

Example: Voltage-Controlled Attenuator If Kn=500mA/V2, VTN=1V, R=2k and VGS = 1, 1.5, 2 V: To maintain triode region operation, or NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: inversion layer change**

If we increase vDS , and it’s no more vDS << VGS - VTN = VOV (triode region limit), it starts influencing the depth of induced inversion layer, for which we need VGS > VTN. VOV - overdrive voltage NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: inversion layer change**

If we increase vDS , and it’s no more vDS << VGS - VTN = VOV (triode region limit), it starts influencing the depth of induced inversion layer, for which we need VGS > VTN. VOV - overdrive voltage vDS = VOV - pinch-off voltage, saturation region begins NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Saturation Region**

What is the current in saturation region? When vDS increases above triode region limit, channel region akmost disappears, MOSFET also said to be pinched-off. Current saturates at (almost) constant value, independent of vDS. is also called saturation or pinch-off voltage. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Saturation Region**

Substituting vDS = vGS - VTN into previous equation for drain current, we get When vDS increases above triode region limit, channel region akmost disappears, MOSFET also said to be pinched-off. Current saturates at (almost) constant value, independent of vDS. Saturation region operation mostly used for analog amplification. is also called saturation or pinch-off voltage. Example here NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: iv-characteristic**

NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Region Summary**

If vDS << VGS - VTN MOSFET is in linear portion of the triode region Triode NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Region Summary**

If vDS << VGS - VTN MOSFET is in linear portion of the triode region If vDS < VGS - VTN MOSFET is in quadratic portion of the triode region NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor: Region Summary**

If vDS << VGS - VTN MOSFET is in linear portion of the triode region If vDS < VGS - VTN MOSFET is in quadratic portion of the triode region If vDS < VGS - VTN MOSFET is in saturation region and current saturates at (almost) constant value, independent of vDS. Discuss how to build the iv graph NJIT ECE271 Dr. Serhiy Levkov

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**Transconductance of a MOS Device**

Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage NJIT ECE271 Dr. Serhiy Levkov

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**Transconductance of a MOS Device**

Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage Taking the derivative of the expression for the drain current in saturation region, NJIT ECE271 Dr. Serhiy Levkov

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**Transconductance of a MOS Device**

Transconductance is the important characteristics that relates the change in drain current to a change in gate-source voltage Taking the derivative of the expression for the drain current in saturation region, The larger the device transconductance, the more gain we can expect from the amplifier that uses the transistor. Transconductance is inverse to the Ron defined earlier and slightly differently. NJIT ECE271 Dr. Serhiy Levkov

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**Channel-Length Modulation**

On the previous iv-characteristics, the saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so. NJIT ECE271 Dr. Serhiy Levkov

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**Channel-Length Modulation**

On the previous iv-characteristics, the saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so. As vDS increases above vDSAT , length of depleted channel beyond pinch-off point, DL, increases and actual L decreases. NJIT ECE271 Dr. Serhiy Levkov

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**Channel-Length Modulation**

On the previous iv-characteristics, the saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so. As vDS increases above vDSAT , length of depleted channel beyond pinch-off point, DL, increases and actual L decreases. Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat. NJIT ECE271 Dr. Serhiy Levkov

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**Channel-Length Modulation**

On the previous iv-characteristics, the saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so. As vDS increases above vDSAT , length of depleted channel beyond pinch-off point, DL, increases and actual L decreases. Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat. As a result, iD increases slightly with vDS instead of being constant and we can rewrite equation in the form: NJIT ECE271 Dr. Serhiy Levkov

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**Channel-Length Modulation**

On the previous iv-characteristics, the saturation part was horizontal (the current was constant, as vDS increases). However, it’s not exactly so. As vDS increases above vDSAT , length of depleted channel beyond pinch-off point, DL, increases and actual L decreases. Since L is in denominator of the current expression, it compensate slightly the general increase of resistivity, which normally makes the curve flat. As a result, iD increases slightly with vDS instead of being constant and we can rewrite equation in the form: where l is the channel length modulation parameter, depends on manufacturing and L. Va – Early voltage. NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement and Depletion Mode MOSFETS**

The MOSFETS transistors can be of two types: enhancement mode when VTN > 0 NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement and Depletion Mode MOSFETS**

The MOSFETS transistors can be of two types: enhancement mode when VTN > 0 depletion mode when VTN < 0 (the NMOS transistors considered so far were of enhancement type.) NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement and Depletion Mode MOSFETS**

The MOSFETS transistors can be of two types: enhancement mode when VTN > 0 depletion mode when VTN < 0 (the NMOS transistors considered so far were of enhancement type.) The depletion mode devices are fabricated by ion implantation process used to form a built-in n-type channel in device to connect source and drain by a resistive channel. NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement and Depletion Mode MOSFETS**

The MOSFETS transistors can be of two types: enhancement mode when VTN > 0 depletion mode when VTN < 0 (the NMOS transistors considered so far were of enhancement type.) The depletion mode devices are fabricated by ion implantation process used to form a built-in n-type channel in device to connect source and drain by a resistive channel. In such case, a non-zero drain current exists for vGS=0, and a negative vGS required to turn device off. NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement and Depletion Mode MOSFETS**

The MOSFETS transistors can be of two types: enhancement mode when VTN > 0 depletion mode when VTN < 0 (the NMOS transistors considered so far were of enhancement type.) The depletion mode devices are fabricated by ion implantation process used to form a built-in n-type channel in device to connect source and drain by a resistive channel. In such case, a non-zero drain current exists for vGS=0, and a negative vGS required to turn device off. Depletion mode – because negative voltage has to be applied to the gate to deplete the n-type channel and eliminate the current path between the source and the drain. NJIT ECE271 Dr. Serhiy Levkov

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**Output and Transfer Characteristics of MOSFETS**

A MOSFET has one output variable – the drain-source current , that depends on two input variables – drain-source voltage and gate-source voltage (VGS is usually is a control variable). NJIT ECE271 Dr. Serhiy Levkov

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**Output and Transfer Characteristics of MOSFETS**

A MOSFET has one output variable – the drain-source current , that depends on two input variables – drain-source voltage and gate-source voltage (VGS is usually is a control variable). Two types of iv-curves are used to describe a MOSFET device fully: output (drain) curve (DS current vs. DS voltage for a fixed GS voltage) (the earlier considered characteristics were drain curves) NJIT ECE271 Dr. Serhiy Levkov

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**Output and Transfer Characteristics of MOSFETS**

A MOSFET has one output variable – the drain-source current , that depends on two input variables – drain-source voltage and gate-source voltage (VGS is usually is a control variable). Two types of iv-curves are used to describe a MOSFET device fully: output (drain) curve (DS current vs. DS voltage for a fixed GS voltage) (the earlier considered characteristics were drain curves) transfer curve (DS current vs. GS voltage for a fixed DS voltage, f.i. sat.) Curves show that the enhancement mode device turns on at VGS = 2, while the depletion mode device turns on at VGS = -2. Example here NJIT ECE271 Dr. Serhiy Levkov

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**Body Effect or Substrate Sensitivity**

So far it was assumed that the source-bulk voltage vSB , is zero, which means that a MOSFET is a three terminal device. Quite often vSB , especially in ICs is not zero.. Non-zero vSB changes threshold voltage. This is called substrate sensitivity and is modeled by where VTO - zero substrate bias for VTN (V) g - body-effect parameter ( )m, determines the intensity of the body effect 2FF - surface potential parameter (V), typically 0.6V. NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Summary (output characteristics)**

NJIT ECE271 Dr. Serhiy Levkov

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**PMOS Transistors Structure (Enhancement-Mode)**

NMOS p-type source and drain regions in n-type substrate. n-type source and drain regions in p-type substrate. NJIT ECE271 Dr. Serhiy Levkov

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**PMOS Transistors Structure (Enhancement-Mode)**

NMOS P-type source and drain regions in n-type substrate. vGS < 0 required to create p-type inversion layer in channel region N-type source and drain regions in p-type substrate. vGS > 0 required to create n-type inversion layer in channel region NJIT ECE271 Dr. Serhiy Levkov

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**PMOS Transistors Structure (Enhancement-Mode)**

NMOS P-type source and drain regions in n-type substrate. vGS < 0 required to create p-type inversion layer in channel region For current flow, vGS<vTP N-type source and drain regions in p-type substrate. vGS > 0 required to create n-type inversion layer in channel region For current flow, vGS > vTN NJIT ECE271 Dr. Serhiy Levkov

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**PMOS Transistors Structure (Enhancement-Mode)**

NMOS P-type source and drain regions in n-type substrate. vGS < 0 required to create p-type inversion layer in channel region For current flow, vGS<vTP To maintain reverse bias on diodes of source-substrate and drain-substrate junctions: vSB < 0 and vDB < 0 N-type source and drain regions in p-type substrate. vGS > 0 required to create n-type inversion layer in channel region For current flow, vGS > vTN To maintain reverse bias on the diodes of source-substrate and drain-substrate junctions: vSB >0 and vDB >0 NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement-Mode PMOS Transistors: Output Characteristics**

For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement-Mode PMOS Transistors: Output Characteristics**

For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement-Mode PMOS Transistors: Output Characteristics**

For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS NJIT ECE271 Dr. Serhiy Levkov

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**Enhancement-Mode PMOS Transistors: Output Characteristics**

For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS For , transistor is off (note that on the diagram it’s vSG = - vGS). NJIT ECE271 Dr. Serhiy Levkov

85
**Enhancement-Mode PMOS Transistors: Output Characteristics**

For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS For , transistor is off (note that on the diagram it’s vSG = - vGS). For more negative vGS, drain current increases in magnitude. NJIT ECE271 Dr. Serhiy Levkov

86
**Enhancement-Mode PMOS Transistors: Output Characteristics**

For the PMOS transistor, all parameters and behavior are inverse of NMOS transistor. Thus the output characteristics of PMOS are the complete inverse of those of NMOS Often, they are shown in the inverted scale and then they look very similar to the characteristics of NMOS For , transistor is off (note that on the diagram it’s vSG = - vGS). For more negative vGS, drain current increases in magnitude. PMOS is in triode region for small (absolute) values of VDS and in saturation for larger values (note that on the diagram it’s more negative to the right). NJIT ECE271 Dr. Serhiy Levkov

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NMOS Summary (model) For the enhancement-mode NMOS transistor, VTN > 0. For the depletion-mode NMOS, VTN < 0. NJIT ECE271 Dr. Serhiy Levkov

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PMOS Summary (model) For the enhancement-mode PMOS transistor, VTP < 0. For the depletion-mode PMOS, VTP > 0. NJIT ECE271 Dr. Serhiy Levkov

89
**NMOS and PMOS Summary (regions of operation)**

NJIT ECE271 Dr. Serhiy Levkov

90
**NMOS and PMOS Summary (terminal voltages)**

NJIT ECE271 Dr. Serhiy Levkov

91
**Short Summary of MOSFET (1)**

A MOSFET is a 3 terminal (Gate, Source, Drain) or 4 terminal (Gate, Source, Drain, Body) electronic device -- it has input (usually vGS) and output (usually iD). The basic function of all transistors - an input voltage is used to provide the change in the output current (or voltage): the change in output can be much bigger then the change in the input - amplifier the change in output can be to turn it on or off – digital gate There are two types of MOSFET : PMOS and NMOS Both types exist in two modes: Enhancement and Depletion. NMOS enhancement mode: the output current (the inversion channel) may exist only when input (vGS ) is positive (>0). NMOS depletion mode: the output current (the inversion channel) may exist when input (vGS ) is zero, requires to apply vGS <0 to shut the current). PMOS is pretty much the complete inverse of NMOS. NJIT ECE271 Dr. Serhiy Levkov

92
**Short Summary of MOSFET (2)**

NMOS Body: p-substrate Source, Drain: n+ Inversion (conduction) layer: n PMOS Body: n-substrate Source, Drain: p+ Inversion (conduction) layer: p E-NMOS Channel (drain current exists when vGS > 0) VTN > 0 D-NMOS Channel (drain current exists when vGS = 0) VTN <= 0 E-PMOS Channel (drain current exists when vGS < 0) VTP < 0 D-PMOS Channel (drain current exists when vGS = 0) VTP >= 0 NJIT ECE271 Dr. Serhiy Levkov

93
**Short Summary of MOSFET (3)**

MOSFET is a symmetrical device – D and S are interchangeable. MOSFET is fully described by two characteristics: - input-output or transfer characteristic: (iD - vGS or vDS - vGS ) - output characteristic: (iD – vDS ) All four types of MOSFET may operate in three regions: - cutoff : output current is 0 - triode: output current almost linearly depends on output voltage vDS (like in resistor) - saturation: output current almost does not depend on DS voltage vDS (like in diode) Transfer characteristics Output characteristics NJIT ECE271 Dr. Serhiy Levkov

94
**MOSFET Circuit Symbols**

(g) and (i) are the most commonly used symbols in VLSI logic design. MOS devices are symmetric. In NMOS, n+ region at higher voltage is the drain. In PMOS p+ region at lower voltage is the drain NJIT ECE271 Dr. Serhiy Levkov

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MOSFET Analysis Depending on the type of application, a MOSFET may be put into one of three regions of operation by setting its operating Q-point NJIT ECE271 Dr. Serhiy Levkov

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MOSFET Analysis Depending on the type of application, a MOSFET may be put into one of three regions of operation by setting its operating Q-point. For binary logic application the transistor acts like an “on-off” switch and the Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for the output characteristic or at the ends of transfer characteristic. NJIT ECE271 Dr. Serhiy Levkov

97
MOSFET Analysis Depending on the type of application, a MOSFET may be put into one of three regions of operation by setting its operating Q-point. For binary logic application the transistor acts like an “on-off” switch and the Q-point is set in ether cut-off region (“off”) or in the triode region (“on”) for the output characteristic or at the ends of transfer characteristic. For amplifier application, the Q-point is set in the saturation region for the output characteristic or in the middle (high) point of the transfer characteristic NJIT ECE271 Dr. Serhiy Levkov

98
**MOSFET Analysis: logic inverter example**

For the low values of input vGS (binary 0) the MOSFET is off, iD =0 and vDS = vout = 5V binary 1. = 0 = 5 =low NJIT ECE271 Dr. Serhiy Levkov

99
**MOSFET Analysis: logic inverter example**

For vGS =5V (binary 1) the MOSFET is on, iD is high, and the output voltage vDS = vout = 0.65V binary 0. =high =0.6 = 5 NJIT ECE271 Dr. Serhiy Levkov

100
**MOSFET Analysis: logic inverter example**

For the low values of input vGS (binary 0) the MOSFET is off, iD =0 and vDS = vout = 5V binary 1. For vGS =5V (binary 1) the MOSFET is on, iD is high, and the output voltage vDS = vout = 0.65V binary 0. = 0 =high = 5 =0.6 =low = 5 NJIT ECE271 Dr. Serhiy Levkov

101
**MOSFET Analysis: amplifier example**

For the amplifier, the Q-point created by vGS = 2.5V is located at the high slope region of transfer characteristic and at the saturation region of the 2.5V curve. =2. 5 NJIT ECE271 Dr. Serhiy Levkov

102
**MOSFET Analysis: amplifier example**

For the amplifier, the Q-point created by vGS = 2.5V is located at the high slope region of transfer characteristic and at the saturation region of the 2.5V curve. A small AC signal is added to vary the gate voltage about vGS = 2.5V, which causes the drain current to change significantly and amplified replica of the input appears at the drain. =2. 5 NJIT ECE271 Dr. Serhiy Levkov

103
**MOSFET Analysis: load line example**

Thevenin equivalent From KVL for the right loop: vDD - vDS - iD RD = 0 iD = (vDD - vDS )/RD Setting two different values for vDS (5V and 3V for example) two points can be obtained and the load line drawn. Nonlinear element NJIT ECE271 Dr. Serhiy Levkov

104
**MOSFET Analysis: load line example**

Thevenin equivalent From KVL for the right loop: vDD - vDS - iD RD = 0 iD = (vDD - vDS )/RD Setting two different values for vDS (5V and 3V for example) two points can be obtained and the load line drawn. Intersection with the transistor iv-curve gives the Q-point, which, of course, depends on the input vGS. Conclusion The same device in the similar circuits may behave differently depending on the ‘biasing‘ – DC voltages applied to different terminals of MOSFET. The ‘signal’ then, is actually comprised of relatively small changes in the DC current and/or voltage bias. Nonlinear element NJIT ECE271 Dr. Serhiy Levkov

105
**Bias Analysis Approach**

The previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: NJIT ECE271 Dr. Serhiy Levkov

106
**Bias Analysis Approach**

The previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) NJIT ECE271 Dr. Serhiy Levkov

107
**Bias Analysis Approach**

The previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) Use circuit analysis to find VGS (left, input loop) NJIT ECE271 Dr. Serhiy Levkov

108
**Bias Analysis Approach**

The previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) Use circuit analysis to find VGS (left, input loop) Use VGS to calculate ID, and ID to find VDS (right, output loop) NJIT ECE271 Dr. Serhiy Levkov

109
**Bias Analysis Approach**

The previous examples shows the importance of biasing for the desired operation of MOSFET. Because of nonlinearity of characteristics and substantial difference in operation region equations (different equations used), iterative approach is used: Assume an operation region (generally the saturation region) Use circuit analysis to find VGS (left, input loop) Use VGS to calculate ID, and ID to find VDS (right, output loop) Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE : An enhancement-mode device with VDS = VGS is always in saturation. Why? For pinch off: VDS >= VGS - VTN . If VDS = VGS , then VDS >= VDS - VTN , or VTN >= 0, which is always true for E-MOS device. NJIT ECE271 Dr. Serhiy Levkov

110
**Bias Analysis 1- Constant GS Voltage Biasing (1)**

Problem: Find Q-pt (ID, VDS , VGS) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Do this example on the board NJIT ECE271 Dr. Serhiy Levkov

111
**Bias Analysis 1- Constant GS Voltage Biasing (1)**

Problem: Find Q-pt (ID, VDS , VGS) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. IG=IB=0. NJIT ECE271 Dr. Serhiy Levkov

112
**Bias Analysis: Ex.1- Constant GS Voltage Biasing (1)**

Problem: Find Q-pt (ID, VDS , VGS) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. IG=IB=0. Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. NJIT ECE271 Dr. Serhiy Levkov

113
**Bias Analysis 1- Constant GS Voltage Biasing (1)**

Problem: Find Q-pt (ID, VDS , VGS) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. IG=IB=0. Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS from the input loop, and then use this to find ID. NJIT ECE271 Dr. Serhiy Levkov

114
**Bias Analysis 1- Constant GS Voltage Biasing (1)**

Problem: Find Q-pt (ID, VDS , VGS) without and with the channel-length modulation ( and ). Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region. Assumption: 1. Transistor is saturated. 2. IG=IB=0. Analysis: Simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage. Find VGS from the input loop, and then use this to find ID. With ID, we can then calculate VDS using the output loop NJIT ECE271 Dr. Serhiy Levkov

115
**Bias Analysis 1- Constant GS Voltage Biasing (1)**

The left (input) loop. Since IG=0: Then, from the transistor equation: NJIT ECE271 Dr. Serhiy Levkov

116
**Bias Analysis 1- Constant GS Voltage Biasing (1)**

The right (output) loop: Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (50.0 mA, 5.0 V) with VGS= 3.0V Discussion. The obtained result is proportional to K and to the square of VTN , thus Q-pt. is quite sensitive to the parameter fluctuation of the device, so this circuit is not very used. The left (input) loop. Since IG=0: Then, from the transistor equation: NJIT ECE271 Dr. Serhiy Levkov

117
**Bias Analysis 1- Constant GS Voltage Biasing (2)**

Now let’s repeat the same problem taking into account channel length modulation. Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (54.5 mA, 4.55 V) with VGS= 3.00 V NJIT ECE271 Dr. Serhiy Levkov

118
**Bias Analysis 1- Constant GS Voltage Biasing (2)**

Now let’s repeat the same problem taking into account channel length modulation. Discussion. The bias levels have changed by about 10%. Typically, component values will vary more than this, so there is little value in including effects in most circuits. Check:VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (54.5 mA, 4.55 V) with VGS= 3.00 V NJIT ECE271 Dr. Serhiy Levkov

119
**Bias Analysis 1- Constant GS Voltage Biasing (3)**

Load Line Analysis. Problem: Find Q-pt (ID, VDS , VGS) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. IG=IB=0. Do we need assumption for the transistor region of operation? NJIT ECE271 Dr. Serhiy Levkov

120
**Bias Analysis 1- Constant GS Voltage Biasing (3)**

Load Line Analysis. Problem: Find Q-pt (ID, VDS , VGS) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. IG=IB=0. 2. No need for region assumption, will find solution directly. NJIT ECE271 Dr. Serhiy Levkov

121
**Bias Analysis 1- Constant GS Voltage Biasing (3)**

Load Line Analysis. Problem: Find Q-pt (ID, VDS , VGS) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. IG=IB=0. 2. No need for region assumption, will find solution directly. Analysis: First, simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage NJIT ECE271 Dr. Serhiy Levkov

122
**Bias Analysis 1- Constant GS Voltage Biasing (3)**

Load Line Analysis. Problem: Find Q-pt (ID, VDS , VGS) Approach: Find an equation for the load line. Use this to find Q-pt at intersection of load line with device characteristic. Assumptions: 1. IG=IB=0. 2. No need for region assumption, will find solution directly. Analysis: First, simplify circuit with Thevenin transformation to find VEQ and REQ for gate-bias voltage The left (input) loop. Since IG=0: NJIT ECE271 Dr. Serhiy Levkov

123
**Bias Analysis 1- Constant GS Voltage Biasing (3)**

Load Line Analysis. From the KVL for the right loop, load line becomes Check: The load line approach agrees with previous calculation. Q-pt: (50.0 mA, 5.00 V) with VGS= 3.00 V Discussion: Q-pt is clearly in the saturation region. Graphical load line is good visual aid to see device operating region. @VDS=0, ID=100uA, @ID=0, VDS=10V Plotting on device characteristic yields Q-pt at intersection with VGS = 3V device curve. NJIT ECE271 Dr. Serhiy Levkov

124
**Bias Analysis 2 - Four-Resistor Biasing (1)**

Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage Problem: Find Q-pt (ID, VDS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, IG=IB=0 Do this example on the board NJIT ECE271 Dr. Serhiy Levkov

125
**Bias Analysis 2 - Four-Resistor Biasing (1)**

Left loop. Since IG=0, NJIT ECE271 Dr. Serhiy Levkov

126
**Bias Analysis 2 - Four-Resistor Biasing (1)**

Solution: If VGS= , VGS<VTN and MOSFET will be cut-off. Thus and ID= 34.4 mA Left loop. Since IG=0, NJIT ECE271 Dr. Serhiy Levkov

127
**Bias Analysis 2 - Four-Resistor Biasing (1)**

Solution: If VGS= , VGS<VTN and MOSFET will be cut-off. Thus and ID= 34.4 mA Right loop. Left loop. Since IG=0, We have VDS >VGS-VTN . Hence saturation region assumption is correct. Q-pt: (34.4 mA, 6.08 V) with VGS= 2.66 V NJIT ECE271 Dr. Serhiy Levkov

128
**Bias Analysis 2 - Four-Resistor Biasing (2) Body Effect**

In previous example, the body terminal was connected to the source, so VSB = 0. Now let’s consider the case with Iterative solution can be found by following steps: Estimate value of ID and use it to find VGS and VSB Use VSB to calculate VTN Find ID’ using last equation If ID’ is not same as original ID estimate, start again. NJIT ECE271 Dr. Serhiy Levkov

129
**Bias Analysis 2 - Four-Resistor Biasing (2) Body Effect**

The iteration sequence leads to ID= 88.0 mA, VTN = 1.41 V, We obtained that VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (88.0 mA, 6.48 V) Check: VDS > VGS - VTN, therefore still in active region. Discussion: Body effect has decreased current by 12% and increased threshold voltage by 40%. NJIT ECE271 Dr. Serhiy Levkov

130
**Bias Analysis 3 – Two Resistor (saturation)**

Assumption: 1. IG=IB=0. 2.Transistor is saturated since VDS=VGS Do this example on the board NJIT ECE271 Dr. Serhiy Levkov

131
**Bias Analysis 3 – Two Resistor (saturation)**

Assumption: 1. IG=IB=0. 2.Transistor is saturated since VDS=VGS Analysis. No need for input loop: VDS=VGS Output loop: NJIT ECE271 Dr. Serhiy Levkov

132
**Bias Analysis 3 – Two Resistor (saturation)**

If VGS= , VGS<VTN and MOSFET will be cut-off. Thus Assumption: 1. IG=IB=0. 2.Transistor is saturated since VDS=VGS Analysis. No need for input loop: VDS=VGS Output loop: and ID= 130 mA We obtained VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (130 mA, 2.00 V) NJIT ECE271 Dr. Serhiy Levkov

133
**Discussion of Four and Two-Resistor Biasing**

Four resistor Provide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region in amplifier circuits. Two-resistor Uses lesser components that four-resistor biasing and also isolates drain and gate terminals. Feedback mechanism. Suppose, for some reason ID begins to increase. From it follows that VGS has to decrease, since Vg is constant. This will decrease the current ID due to current equation, thus restoring the existing state. NJIT ECE271 Dr. Serhiy Levkov

134
**Bias Analysis 4 – One Resistor (triode)**

Assumption: 1. IG=IB=0 2. Transistor is saturated. Analysis. Left loop: VGS=VDD=4 V Do this example on the board NJIT ECE271 Dr. Serhiy Levkov

135
**Bias Analysis 4 – One Resistor (triode)**

Right loop: Assumption: 1. IG=IB=0 2. Transistor is saturated. Analysis. Left loop: VGS=VDD=4 V NJIT ECE271 Dr. Serhiy Levkov

136
**Bias Analysis 4 – One Resistor (triode)**

Right loop: We obtained VDS<VGS -VTN. Hence, saturation region assumption is incorrect. Assume the triode region and use the triode region equation: Assumption: 1. IG=IB=0 2. Transistor is saturated. Analysis. Left loop: VGS=VDD=4 V and ID=1.06 mA We obtained VDS<VGS -VTN, transistor is in triode region Q-pt:(1.06 mA, 2.3 V) NJIT ECE271 Dr. Serhiy Levkov

137
**Bias Analysis 5 - Two-Resistor, PMOST**

Right loop: Since VGS= V is more than VTP= -2 V, we take VGS = V Then we can calculate ID = 52.5 mA. Check: Assumption: 1. IG=IB=0 2. Transistor is saturated: VDS=VGS Analysis. Left loop: no need, VDS=VGS Hence saturation assumption is correct. Q-pt: (52.5 mA, V) Do this example on the board NJIT ECE271 Dr. Serhiy Levkov

138
**Junction Field-Effect Transistors (JFET)**

NJIT ECE271 Dr. Serhiy Levkov

139
**Junction Field-Effect Transistors (JFET)**

MOSFET devices are called FET because electric field is used to control the shape and hence the conductivity of the channel of one type charge carrier (p or n) in semiconductor device. There is another type of FET, which is not using MOS capacitor structure, however utilizes the electric filed effect: Junction Field-Effect Transistor. Less prevalent than MOSFET, JFET have many uses, especially in analog RF applications. Can be of two types: n-channel and p-channel JFET. n-channel JFET consists of: n-type semiconductor block that houses the channel region in n-channel JFET. pn junction - forms the gate. Source and drain terminals Like a diode with enlarged n-type section and two n-terminals. NJIT ECE271 Dr. Serhiy Levkov

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JFET Structure With no bias applied, a resistive channel exists. The current enters channel at the drain and exits at source. The resistance of the drain-source channel is controlled by changing the physical width of the channel through modulation of the depletion layers around pn-junctions (like squeezing a garden hose) Application of reverse bias to the gate-channel diodes causes the depletion layer to widen, reducing the channel width and decreasing the current. JFET is inherently a depletion-mode device – a voltage must be applied to turn the device off. In triode region, JFET is a voltage-controlled resistor, r - resistivity of channel L - channel length W - channel width between pn junction depletion regions t - channel depth NJIT ECE271 Dr. Serhiy Levkov

141
**JFET: applying Gate-Source voltage**

vGS = 0. The channel width is W. It can conduct current well if vDS is applied. NJIT ECE271 Dr. Serhiy Levkov

142
**JFET: applying Gate-Source voltage**

vGS = 0. The channel width is W. It can conduct current well if vDS is applied. VP < vGS <0. The depletion layers width is increased. The channel width W’ < W, and channel resistance increases. Gate-source junction is reverse-biased, iG almost 0. NJIT ECE271 Dr. Serhiy Levkov

143
**JFET: applying Gate-Source voltage**

vGS = 0. The channel width is W. It can conduct current well if vDS is applied. VP < vGS <0. The depletion layers width is increased. The channel width W’ < W, and channel resistance increases. Gate-source junction is reverse-biased, iG almost 0. vGS = VP < 0. The depletion layer is max. Channel width – zero, region is pinched-off, channel resistance is infinite. NJIT ECE271 Dr. Serhiy Levkov

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**JFET: applying Drain-Source voltage**

With constant vGS, depletion region near drain increases with vDS NJIT ECE271 Dr. Serhiy Levkov

145
**JFET: applying Drain-Source voltage**

With constant vGS, depletion region near drain increases with vDS At vDSP = vGS - VP , channel is totally pinched-off; iD is saturated. (the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain) NJIT ECE271 Dr. Serhiy Levkov

146
**JFET: applying Drain-Source voltage**

With constant vGS, depletion region near drain increases with vDS At vDSP = vGS - VP , channel is totally pinched-off; iD is saturated. (the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain) JFET also suffers from channel-length modulation like MOSFET at larger values of vDS. NJIT ECE271 Dr. Serhiy Levkov

147
**JFET: applying Drain-Source voltage**

With constant vGS, depletion region near drain increases with vDS At vDSP = vGS - VP , channel is totally pinched-off; iD is saturated. (the current does not stop: electrons are accelerated down the channel (V is large), are injected into the depletion region and swept to the drain) JFET also suffers from channel-length modulation like MOSFET at larger values of vDS. Simulation: NJIT ECE271 Dr. Serhiy Levkov

148
**N-Channel JFET i-v Characteristics**

The JFET iv-characteristics are remarkably similar to the MOSFET characteristics (virtually identical). Transfer Characteristics Output Characteristics NJIT ECE271 Dr. Serhiy Levkov

149
**N-Channel JFET i-v equations**

Equations are similar to MOSFET except written slightly differently For all regions : In cutoff region: In Triode region: In pinch-off region: Explanation: Typically: NJIT ECE271 Dr. Serhiy Levkov

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P-Channel JFET Polarities of n- and p-type regions of the n-channel JFET are reversed to get the p-channel JFET. Channel current direction and operating bias voltages are also reversed. NJIT ECE271 Dr. Serhiy Levkov

151
**JFET Circuit Symbols n-channel p-channel**

JFET structures are symmetric like MOSFETs. Source and drain determined by circuit voltages. NJIT ECE271 Dr. Serhiy Levkov

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**JFET n-Channel Model Summary**

NJIT ECE271 Dr. Serhiy Levkov

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**JFET p-Channel Model Summary**

NJIT ECE271 Dr. Serhiy Levkov

154
**Biasing JFET (1) N-channel JFET Depletion-mode MOSFET**

Assumptions: Gate-channel junction is reverse-biased, reverse leakage current of gate, IG = 0 NJIT ECE271 Dr. Serhiy Levkov

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Biasing JFET (2) DIY NJIT ECE271 Dr. Serhiy Levkov

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**Biasing JFET (3) Region Assumption: JFET is pinched-off (saturation)**

Since VGS = V is less than VP= -5 V , we take VGS = V (n-channel type!) and, ID = IS = 1.91 mA. Output loop: Since VGS = V is less than VP= -5 V , we take VGS = V (n-channel type!) and, ID = IS = 1.91 mA. Output loop: VDS =6.72 VDS >VGS -VP. Hence pinch-off region assumption is correct and gate-source junction is reverse-biased by 1.91V. Q-pt: (1.91 mA, 6.27 V) VDS >VGS -VP. Hence pinch-off region assumption is correct and gate-source junction is reverse-biased by 1.91V. Q-pt: (1.91 mA, 6.27 V) NJIT ECE271 Dr. Serhiy Levkov

157
**Internal Capacitances in Electronic Devices**

Limit high-frequency performance of the electronic device they are associated with. Limit switching speed of circuits in logic applications Limit frequency at which useful amplification can be obtained in amplifiers. MOSFET capacitances depend on operation region and are non-linear functions of voltages at device terminals. NJIT ECE271 Dr. Serhiy Levkov

158
**NMOS Transistor Capacitances: Triode Region**

Cox” =Gate-channel capacitance per unit area(F/m2). CGC =Total gate channel capacitance. CGS = Gate-source capacitance. CGD =Gate-drain capacitance. CGSO and CGDO = overlap capacitances (F/m). CSB = Source-bulk capacitance. CDB = Drain-bulk capacitance. AS and AD = Junction bottom area capacitance of the source and drain regions. PS and PD = Perimeter of the source and drain junction regions. NJIT ECE271 Dr. Serhiy Levkov

159
**NMOS Transistor Capacitances: Saturation Region**

Drain no longer connected to channel NJIT ECE271 Dr. Serhiy Levkov

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**NMOS Transistor Capacitances: Cutoff Region**

Conducting channel region completely gone. CGB = Gate-bulk capacitance CGBO = gate-bulk capacitance per unit width. NJIT ECE271 Dr. Serhiy Levkov

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JFET Capacitances CGD and CGS are determined by depletion-layer capacitances of reverse-biased pn junctions forming gate and are bias dependent. NJIT ECE271 Dr. Serhiy Levkov

162
**SPICE Model for NMOS Transistor**

Typical default values used by SPICE: Kn or Kp = 20 mA/V2 g = 0 l = 0 VTO = 1 V mn or mp = 600 cm2/V.s 2FF = 0.6 V CGDO=CGSO=CGBO=CJSW= 0 Tox= 100 nm NJIT ECE271 Dr. Serhiy Levkov

163
**SPICE Model for JFET Typical default values used by SPICE: Vp = -2 V**

l = CGD = CGD = 0 Transconductance parameter BETA BETA = IDSS/VP2 = 100 mA/V2 NJIT ECE271 Dr. Serhiy Levkov

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DMT121 – ELECTRONIC DEVICES

DMT121 – ELECTRONIC DEVICES

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