Presentation on theme: "BEPCII RF POWER SYSTEM RF group, IHEP. 2004 Sep ~ 2005. April 1.The 1 st transmitter had finished installing,commissioning and SAT (Site Acceptance Test)."— Presentation transcript:
2004 Sep ~ 2005. April 1.The 1 st transmitter had finished installing,commissioning and SAT (Site Acceptance Test). 2.The 1 st circulator had finished installing and commissioning. 3.The equipments and components for the 2 nd transmitter had been prepared in IHEP.
2005.July ~ 2005. Nov. East Hall reconstruction for 2 nd. Power Sys Setting up Cooling Water, Cooling Air and Electricity
2005.7 th. Nov ~ 2006. 23th. Jan Installation and commissioning in East Hall for the 2 nd transmitter.
Some problems 1. Some certain signals always tripped because of something wrong in the isolation transformer. We replaced the isolation transformer with a new one. 2. During 50 hours 250kW high power test, after first 24 hours, we had a electricity shut-down. Transmitter was OK and restarted very soon.
Satisfied Result Frequency ： 499.8MHz @Bandwidth : +/- 1MHz Pout≥ 250kW η≥60% RF Gain ： Gain ≥ 40dB @ 250kW Harmonic: （ 499.8MHz×2 ）： -39.66dB （ 499.8MHz×3 ）： -61.17dB At 250kW, output power is stabling between － 0.001dB and 0.002dB ， phase stabling between － 0.2 0 and 0.02 0 。
The result diagram: Return Loss vs. Sliding short position
2006 1 rd. Mar ~ 2006 25 th Mar West hall wave guide installed and loaded 150kW for 1 month to be prepared for Coupler high power test
2006 26 th. Mar ~ 2006 25 th. Apr 1.Transmitter EPICS ICS extension 2.Interlock system for SCC 3.Operation mode for m1: Operation m2: Coupler high power test m3: SCC high power test
Test Plan 29 th. April 2006 conditioning in Mode2 10 th. May 2006 conditioning in Mode3 June 2006 moving into tunnel and test again
Coupler high power test Signals for mode2 has been connected to IOC computer and interlock system. Signals concerning water, air, temperature, arc, input power, reflected power, person safe. Ready for high power test for coupler.
Control station EPICS (VME, LINUX, VXWORK) FPGA interlock sys. And mode switch.
Signal Relays Locker All hardware signal relays here.
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