1. System Architecture of Detector Control and Safety for the ATLAS Inner Detector Upgrade Didier Ferrère, DPNC Université de Genève Susanne Kersten, Wuppertal University

2. 2 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima New Inner Detector for ATLAS Upgrade Under consideration: Current silicon tracker is expected to smoothly die with an integrated luminosity (< 600 fb -1 ) : Radiation damages and Inefficiencies at high rate. A new ID is foreseen at phase 2 Upgrade of the machine and for data taking in ~2020 The electrical services between the counting rooms and the cavern remain a constraint for the new detector All the hardware for the FE electronics, the DAQ, the power supply and the DCS will have to be renewed The cooling is one of the critical challenges for the future silicon tracker with requested operational temperature down to -40°C All the development has to fit in the framework of the existing ATLAS DAQ, DCS, Trigger with some restrictions under study One ID layout under consideration 4 pixel layers 3 Short-strip layers 2 Long-strip layers

3. 3 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima ATLAS Detector Control System to be Updated Pixel & Strip to be renewed Cooling and ID environment to be renewed The new DCS structure has to fit in the ATLAS GCS

4. 4 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima DCS Motivations The DCS has to be defined as early as possible such it is integrated into the readout architecture together with the powering and the services. Towards the specifications: Define the needs  Use cases (close to current tracker) The detector safety and the interlock to be considered as the 1 st requirement Monitoring sources to be well evaluated Minimize as much as possible the material and the services Optimize the development effort Limit access installation in the cavern  DCS hardware in the counting room Try to define a common Pixel and Strip DCS architecture if possible Search for adequate sensors: Humidity, others? Identify all the topics where early resources may be necessary Define the prototypes for DCS investigations like power monitoring and control Up to 180 kW to control and monitor during the operation in term of power, cooling, and environment across the all ID.

5. 5 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Comments: SMC is located at the stave end and steer 24 hybrids. In total and per stave there are 2 SMCs: one per side. SMC (Super Module Controller) is a hybrid board which integrates the opto, the GBT, the DCS and some power regulations 1 or 2 MCC (Module Controller Chip) steer the data of the 20 chips on a hybrid The service bus is running below the Si-wafers and the front and back detector bias are separated. There are 2 SMCs par Stave/SM electrically separated from the top and bottom side Short Strip Barrel Stave Layout Service bus TTC, Data & DCS fibers PS cable DCS env. IN Cooling InOpto GBT DCS interlock SMC Hybrid Module #1Module #2Module #12 Cooling Out IP Beam Axis * the GBT (Giga Bit Transmission) is a chip for data transmission developed by the CERN PH-ESE group MCC

6. 6 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Pixel Barrel Stave Layout FE GBT*DCS FE Module 0Module 7 End of Stave Card half stave Beam Axis 2 single sided staves sandwiched together back to back GBT*DCS Comments: The construction of the staves varies between the different layers 24 - 32 modules/stave There are 4 Front End chips/detector module The DCS relevant building blocks are half stave/disk sector: up to 16 modules + 1 EoS card For both Pixel and strip two options are considered for the powering: - Serial powering - Parallel powering with 2 DC-DC stages IP * the GBT (Giga Bit Transmission) is a chip for data transmission developed by the CERN PH-ESE group

7. 7 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima ID Upgrade DCS Architecture ID DCS Strip DCSPixel DCS ID DCS Gen? Cool DCS FE DCSDCS Chip Elect. Opto at PS Lines from staves to counting room DCS split at BOC/ROD DCS Data with RO Data DCS at PS Not defined yet! ‘Cooling Interlock’ ‘Strip Module Interlock’ ‘SMC Interlock’ @ « BBIM »@ « SMC » @ PS card @ « BBIM » or Pixel Stave Elect. ‘Pixel Module Interlock’ @ « BBIM » DCS Chip Strip Stave Power SupplyEnv DCS Elect. Env DCS SPI or I2C FE DCS DCS Data with RO Data Opto Lines from staves to counting room

8. 8 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Strip Architecture Overview

9. 9 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Pixel Architecture Overview Distance from interaction point [m] Control room ~100 DCS Master Power Supplies Pixel DCSPixel DAQ Readout Crate diagnostics Interlock Circuit EoS Controller Opto Board symmetric to both sides cable bundle from half stave DCS Environment safety Control – feedback DCS End of Stave Card half staves ~50 Detector volume

10. 10 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Safety Interlock and Monitoring Sources StripPixel Cooling Interlock NTCs / Stave2- Justification Protection against cooling failure - Action Power cut of the corresponding LV & HV stave - Module Interlock NTCs / Stave4816  4 lines Justification Protection against any heat excess. Reasons: Runaway, Cooling failure, contact problem Protection against any heat excess. Reasons: Cooling failure, runaway, contact problem Action Either Disable LV locally or at power supply Power cut of the corresponding LV & HV stave Stave Card Interlock NTCs / Stave21 Justification Protection against excess heating of EoS Card Action Disable the LV power on all the stave Monitoring sources: NTCs, RH sensors, power supplies, FE temp & power.

11. 11 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Interlock and Monitoring of Module NTCs for  Strip

12. 12 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima LV Mod PS Bot HV PS Bot X 9-12 HV PS Top X 9-12 LV Mod PS Top PS Crate DCS I-box NTC-Cooling NTC- SMC I-Cooling/Mod I-SMC-Top I-SMC-Bot I-Modue Top I-Modue Bot Top-side Stave Power-DCS cable Bottom-side Stave Power-DCS cable NTC-Mod (option3) LV SMC PS Bot LV SMC PS Top Combining Interlocks at PS crate – Strip Serial Powering

13. 13 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Interlock and Monitoring of Module NTCs for  Pixel On detector Off detector DCS chip NTC A Interlock Temp. measurement of detector modules: NTCs are supplied from outside In case of environmental temp. measurement, the NTCs will be supplied by the DCS chip Interlock steered in the counting room

14. 14 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Towards a Common Radiation Hard DCS Chip Motivations: - Unification of some DCS hardware across the ATLAS ID - Optimize development effort and cost - Chip should be as flexible as possible in term of use in the all ID volume Main features: Radiation hardness up to 1.3x10 16 1 MeV n eq /cm 2 Have to work with two protocols: I2C/SPI (low frequency), and GBT e-port (40 MHz) Low power when running at low frequency with I2C or SPI: < 0.1W About 32 analog input needed Some DAC for power control and up 17 dig. Out (Bypass for pixel SP + reset) Interlock function based on FSM with programmable temp limits (Strip) SEU protection for all the relevant parts Interlock decision need to be sure Power supply reference for NTCs Analog Mux 32 I2CSPIGBT a1 a32 Vref SCK Din Dout CE SDA SCL FSM VSupplyVRef Alarm flag DAC 1 bit dout ADC 10bit E-link for Slow Control NB: A DCS IC submitted by Wuppertal to study I2C and SPI

15. 15 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima GBT-SCA – Slow Control in a Radiation Hard DCS IC From A. Marchioro On-Detector Custom Electronics & Packaging Radiation Hard Off-Detector Commercial Off-The-Shelf (COTS) Custom Protocol I2C Master SCA Controller SCL SDATA D[0:7] A[0:15] JTAG Master Clock Generation E-Link Monitoring ADC Ch1 Ch2 … Ch16 Monitoring ADC 16 x I2C Buses Memory Interface PIA 4 x PP[0:7] Ext Reset* I2C Master e-Link Controller The “GBT Project” is part of the “Radiation Hard Optical Link Project” which aims at developing a radiation hard bi-directional optical link for use in the LHC upgrade programs

16. 16 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Conclusions The Inner Tracker Upgrade has to be renewed and is under development & prototyping construction based on silicon pixel and strip The DCS has to be designed as a new system to fit with the detector requirements in term of safety and operation as well as with the ATLAS Global Control System The key parameters of such a system are the control of the power and of the temperature of the complete tracker Controllable power is needed at the detector parts using either serial powering or DC-DC conversion New features are proposed for detector diagnostics like including DCS into FE chips Strip and Pixel detectors have different requirements but need to unify system, effort and some hardware parts A single radiation hard DCS IC is one of the illustration of it with some common specifications that are under investigation. GBT-SCA is a possible option now considered Still a lot to investigate in term of steering DCS interlock and information at the counting room and linked to the Power Supply units

17. 17 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Back-up slides

18. 18 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Back-up slides Pixel - Disabling of serial powered modules charge pump: DCS chip produces pulses (between 0 and 3.3 V) C1 is charged to U_GS (2.5 V due to inefficiency) Bonn-Wuppertal Stave emulator system DCS chip is simulated by COBOLT (DCS board with microprocessor)

19. 19 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima DCS chips are running permanently check that there is no temp. interlock check temp of opto board turn on cooling of opto boards turn on power of opto board + monitor its power check temp of modules and EOS turn on cooling of modules turn on power of EOS controller and modules + monitor their power consumption initialize opto board configure modules power consumption → successful configuration start tuning, calibration, etc … of data taking chain Back-up slides Pixel - Power Up Sequence

20. 20 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Back-up slides Strip – DCS Operational Sequences Pre-operationSMC ramp & Opto comModule rampOperation Cooling Interlock Active, Env. data accessible, PS Module Interlock Active, Module temp, local PS accessible DCS Cooling Survey FE DCS, Hybrid power accessible High data volume Possible but not desired Medium data volume > 4.3x10 5 data/day/stave Low data volume > 5x10 4 data/day/stave @ 0.1-1Hz On request Detector Cold From DCS system with option 2 From DAQ with option 1&3 A)B)C)D)

21. 21 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Back-up slides Strip – DCS Operational Sequences Operational phaseOption 1 & 3Option 2 Pre-operation Cooling OFF Access to Env DCS and monitor cooling Interlock NTCs (+ 1 Module side for option 3) Access to Env DCS and monitor cooling interlock NTCs & module temps  Module Interlock active SMC ramp & Opto com Cooling ON Power ramp-up on SMC for Opto settings and com. DCS ON – Monitor module temp + Env  Module Interlock active Power ramp-up on SMC for Opto settings and com. DCS ON – Monitor module temp + Env  Module interlock still active Module ramp Cooling ON Power ramp-up on FE hybrids. Active protection + Bypass (SP) or Power En/Dis (DC-DC) DCS diagnostics accessible Power ramp-up on FE hybrids. Active protection + Bypass (SP) or Power En/Dis (DC-DC) DCS diagnostics accessible Operation Cooling ON Active protection + Bypass (SP) or Power En/Dis (DC-DC) DCS diagnostics accessible Active protection + Bypass (SP) or Power En/Dis (DC-DC) DCS diagnostics accessible E) Module temp failure Cooling ON SP: FE LV + HV inhibit (Case B) DC-DC: Module power disable (Case C-D) SP: FE LV + HV inhibit (Case B) DC-DC: Module power dsiable (Case C-D) F) Cooling failure Cooling OFF All power interlocked! (Case A)

22. 22 D. Ferrère HSTD7, Aug 29th Sept 1st, 2009 in Hiroshima Back-up slides DCS Data & Interlock versus the Construction Phase & Test Hybrid & Module QA Stave QAIntegration & Tests Barrel commissioning ID commissioning Cooling typeWaterWater or evaporative No coolingEvaporative Power typeLocal powerSMC power Module power SMC power (quick tests) Final PS crate SMC and Module power Type of testFE ReadoutFE readout chain GBT-Opt com Conn. tests Full readout PS DCSCustom survey NOFinal system – PS Mon Final system - PS Mon Environmental survey No Connectivity testYes SMC DCSNoYesYes for com testYes Cooling interlock No Yes (Warm cool)Yes (Possibly warm cool) Module interlock Home made NoYes SMC interlockNoHome madeNoYes NB: Modules are never tested un-cooled either individually or on the stave