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CGS 3763 Operating Systems Concepts Spring 2013 Dan C. Marinescu Office: HEC 304 Office hours: M-Wd 11:30 - 12:30 AM.

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Presentation on theme: "CGS 3763 Operating Systems Concepts Spring 2013 Dan C. Marinescu Office: HEC 304 Office hours: M-Wd 11:30 - 12:30 AM."— Presentation transcript:

1 CGS 3763 Operating Systems Concepts Spring 2013 Dan C. Marinescu Office: HEC 304 Office hours: M-Wd 11: :30 AM

2 Last time: Page replacement algorithms Implementation of paging Hit and miss ratios Performance penalties  Today Performance penalties Spatial and temporal locality of reference Virtual memory Page fault handling Working set concept Next time  Class review Reading assignments  Chapter 9 of the textbook Lecture 37 – Wednesday, April 17, 2013 Lecture 382

3 Two-level memory system To understand the effect of the hit/miss ratios we consider only a two level memory system  P  a faster and smaller primary memory  S  A slower and larger secondary memory. The two levels could be: P  L1 cache and S  main memory P  main memory and S  disk Lecture 383

4 The performance of a two level memory The latency L p << L S  L P  latency of the primary device e.g., 10 nsec for RAM  L S  latency of the secondary device, e.g., 10 msec for disk Hit ratio h  the probability that a reference will be satisfied by the primary device. Average Latency (AS)  AS = h x L P + (1-h) L S. Example:  L P = 10 nsec (primary device is main memory)  L S = 10 msec (secondary device is the disk)  Hit ratio h= 0.90  AS= 0.9 x x 10,000,000 = 1,000, nsec~ 1000 microseconds = 1 msec  Hit ratio h= 0.99  AS= 0.99 x x 10,000,000 = 100, nsec~ 100 microseconds = 0.1 msec  Hit ratio h=  AS= x x 10,000,000 = 10, nsec~ 10 microseconds = 0.01 msec  Hit ratio h=  AS= x x 10,000,000 = 1, nsec~ 1 microsecond This considerable slowdown is due to the very large discrepancy (six orders of magnitude) between the primary and the secondary device. Lecture 384

5 The performance of a two level memory (cont’d) Statement: if each reference occurs with equal frequency to a cell in the primary and in the secondary device then the combined memory will operate at the speed of the secondary device. The size Size P << Size S Size S =K x Size P with K large (1/K small)  Size P  number of cells of the primary device  Size S  number of cells of the secondary device Lecture 385

6 Why paging works Locality of reference  once a page is brought to the primary storage it is likely that more items in the page will be referenced. Spatial locality of reference  if an item at displacement k in a page is referenced it is likely that items at displacements around k will be referenced next. Why?  Code -  Data - Temporal locality of reference  if an item at displacement k in a page is referenced it is likely that other items in the page will be reference soon. Why?  Code -  Data - Lecture 386

7 Virtual memory Separation of user logical memory from physical memory.  Only part of the program needs to be in memory for execution  Logical address space can therefore be much larger than physical address space  Allows address spaces to be shared by several processes  Allows for more efficient process creation Virtual memory can be implemented via demand paging Lecture 387

8 Virtual-address space of a process Lecture 388

9 Demand paging Bring a page into memory only when it is needed Less I/O needed Less memory needed Faster response More users Page is needed  reference to it invalid reference  abort not-in-memory  bring to memory Lecture 389

10 Valid-invalid bit With each page table entry a valid–invalid bit is associated (v  in-memory, i  not-in-memory) Initially valid–invalid bit is set to i on all entries Example of a page table snapshot: During address translation, if valid–invalid bit in page table entry is I  page fault v v v v i i i …. Frame #valid-invalid bit page table Lecture 3810

11 Page table when some pages are not in main memory Lecture 3811

12 Page fault handling Page fault  occurs when there is a reference to a page not in the main memory the system. Then the VMM (Virtual Memory Manager) and the MLMM (Multi- Level Memory Management) components of the kernel:  Check if the reference is invalid  abort  If the reference is valid – process the page fault 1. Find an empty frame. 2. Transfer the page from the disk to empty frame. 3. Update the page entry in the page table with the address of the frame. 4. Set validation bit = v in the page table entry of the page. 5. Restart the instruction that caused the page fault. Lecture 3812

13 Handling a page fault Lecture 3813

14 The clock algorithm is used to simulate the LRU algorithm. Keep all the page frames on a circular list in the form of a clock. A hand points to the oldest page. When a page fault occurs, the page being pointed to by the hand is inspected. If its R bit is F, the page is evicted, the new page is inserted into the clock in its place, and the hand is advanced one position. If R is T, it is cleared and the hand is advanced to the next page. This process is repeated until a page is found with R = F. Lecture 3814

15 System components involved in memory management Virtual memory manager – VMM  dynamic address translation Multi level memory management – MLMM  Lecture 3815

16 The modular design VM attempts to translate the virtual memory address to a physical memory address If the page is not in main memory VM generates a page-fault exception. The exception handler uses a SEND to send to an MLMM port the page number The SEND invokes ADVANCE which wakes up a thread of MLMM The MMLM invokes AWAIT on behalf of the thread interrupted due to the page fault. The AWAIT releases the processor to the SCHEDULER thread. Lecture 3816

17 Lecture 3817

18 Working-set model   working-set window  a fixed number of page references Example: 10,000 instruction WSS i (working set of Process P i ) = total number of pages referenced in the most recent  (varies in time)  if  too small will not encompass entire locality  if  too large will encompass several localities  if  =   will encompass entire program D =  WSS i  total demand frames if D > m  Thrashing Policy if D > m, then suspend one of the processes Lecture 3818

19 Working-set model Lecture 3819

20 How to estimate the working set Hardware needed: 1. Interval timer 2. Reference bits. Example:  = 10,000  Timer interrupts after every 5000 time units  Keep in memory 2 bits for each page  Whenever a timer interrupts copy and sets the values of all reference bits to 0  If one of the bits in memory = 1  page in working set Why is this not completely accurate? Improvement = 10 bits and interrupt every 1000 time units Lecture 3820

21 Name resolution in multi- level memories We consider pairs of layers:  Upper level of the pair  primary  Lower level of the pair  secondary The top level managed by the application which generates LOAD and STORE instructions to/from CPU registers from/to named memory locations The processor issues READs/WRITEs to named memory locations. The name goes to the primary memory device located on the same chip as the processor which searches the name space of the on-chip cache (L1 cache), the primary device with the L2 cache as secondary device. If the name is not found in L1 cache name space the Multi-Level Memory Manager (MLMM) looks at the L2 cache (off-chip cache) which becomes the primary with the main memory as secondary. If the name is not found in the L2 cache name space the MLMM looks at the main memory name space. Now the main memory is the primary device. If the name is not found in the main memory name space then the Virtual Memory Manager is invoked Lecture 3821

22 Process creation Virtual memory allows other benefits during process creation: Copy-on-Write (COW)  allows both parent and child processes to initially share the same pages in memory.  If either process modifies a shared page, only then is the page is copied.  COW allows more efficient process creation as only modified pages are copied Lecture 3822

23 Before and after process 1 modifies page C Lecture 3823

24 Memory-mapped files Memory-mapped file I/O allows file I/O to be treated as routine memory access by mapping a disk block to a page in memory A file is initially read using demand paging. A page-sized portion of the file is read from the file system into a physical page. Subsequent reads/writes to/from the file are treated as ordinary memory accesses. Simplifies file access by treating file I/O through memory rather than read() write() system calls Also allows several processes to map the same file allowing the pages in memory to be shared

25 Memory-mapped files


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