Presentation on theme: "MURI Device-level Radiation Effects Modeling Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton School of Engineering."— Presentation transcript:
MURI Device-level Radiation Effects Modeling Hugh Barnaby, Jie Chen, Ivan Sanchez Department of Electrical Engineering Ira A. Fulton School of Engineering Arizona State University
Topics Target of Research Radiation Effect Modeling: A TCAD- based approach Example: Drain-source leakage in deep- submicron bulk CMOS
Goals Model the effects of TID and DD defects on advanced device technologies Identify the continuing and emerging radiation threats to these technologies Model the defects: implement physical models, dynamics of buildup Radiation effects testing (Co 60, neutrons, low temperature testing)
Radiation Concerns Total ionizing dose Displacement damage Single event damage and micro-dose
Device Categories Ultra Small Bulk CMOS Silicon on Insulator (dual gate operation) Strained Silicon CMOS SiGe HBTs ASU has a strong relationship with FreeScale semiconductor.
Effects Oxide Damage and Reliability Defect buildup Leakage Breakdown Annealing and other temperature dependent processes Semiconductor Effects Electrostatics Carrier recombination and removal Mobility effects Annealing and other temperature dependent processes
Testing Co60 -sources ASU (100 rd/s, 1 rd/s, ~10mrd/s) UA (100 rd/s, 10 md/s) Neutron Sources (UA – Triga and Rabbit Reactors) Low temperature Co 60 irradiations (down to 70k)
TCAD Modeling and Simulation PROCESSDEVICECIRCUIT To EDA Process Sim. Device Sim. Circuit Sim. OPTIMIZE ELECTRICAL PERFORMANCE Process and Layout Description Bias Conditions Design OPTIMIZE STRUCTURE GEOMETRY NET DOPING 2D cross section of LOCOS parasitic nMOSFET 2D potential contours in parasitic nMOSFET SRAM Schematic including parasitic nMOSFET element Leakage current vs. drain voltage I leak VdVd POTENTIAL TCAD Flow
Radiation Effects Modeling Total Dose Process and Layout Description Bias Conditions OPTIMIZE GEOMETRY AND PRECURSORS Strain effects, energy to defect conv., doping profiles heating, defect formation, tunneling. Displace. Damage Defect precursors Device carrier transport in dielectric, defect formation and approximations Process
Example: D-S Leakage Due to aggressive scaling into the deep sub-micron, the threat of significant threshold voltage shifts caused by charge buildup in the gate oxide has been reduced. Instead threats have shifted elsewhere, such as drain-to- source leakage caused by charge buildup in the isolation oxide (shallow trench – STI) Polysilicon gate N+ drain N+ Source Leakage + + STI shallow trench isolation oxide Leakage
TID effects on off-state leakage After Lacoe NSREC SC 2003 Increase in off-state leakage (I Vgs = 0V) increases to 100nA after 400 krad of exposure. Problem in SRAM arrays (power, overheating, and failure)
TI-MSC1211 A/D Converter 24-bit Delta-Sigma ADC Internal reference generator Intel 8051 microcontroller Timers Universal asynchronous receiver and transmitter RAM, ROM, and flash memory measure specifications Temperature monitor, RTD (resistant temperature device), mounted on package I supply V supply
Offset Calibration Other specs include: full scale, and ENOB Bit-error output for differential input High frequency data represents noise induced offsets Mean value determined by device mismatch, temp variation, etc.
Supply Current and Temperature Field oxide leakage path Digital Supply Current vs. DOSE Package Temperature vs. DOSE TID leads to increase in operating temperature of device.
Photoemission Analysis Field oxide leakage path V supply Increased power dissipation and die temperature caused by high static current density in pre-charge devices of SRAM array.
Mechanism Increased current density reveals impact of radiation-induced leakage mechanism: the parasitic nMOSFET.
L W L W STI L W L W Parasitic nMOSFET “as drawn” nMOSFET parasitic nMOSFET VTVT V T (0) V T (10 11 ) V T (10 12 ) V T (10 13 ) “as drawn”nFET parasiticnFET Drive current Increasing TID PRE-RAD Due to its greater oxide thickness, the parasitic nMOSFET has a much higher V T and lower drive current compared to “as drawn” device. POST-RAD Due to its greater oxide thickness, oxide-charge buildup in the parasitic nMOSFET is much greater, causing large shifts in V T drive current.
Parasitic nMOSFET Parameters Parasitic nFET “As Drawn” nFET “As Drawn” Parasitic t ox W eff V t Circuit modeling of leakage requires accurate extraction of key parasitic parameters: threshold voltage, effective width, and oxide thickness
2D Modeling Approach Standard 2-edge device DrainSource Gate N ot Cutline 2D Cross-section along cutline Si STI gate uniform oxide charge (N ot ) Modeling on IBM 0.13um 8RF CMOS
2D Modeling Results N ot = 5x10 12 cm 2 (uniform) V gs = 0.2V Combination of N ot, gate bias, and device properties creates electron inversion layer at the STI edge electron inversion layer
Definition of Threshold Voltage Threshold voltage is the gate voltage at which the inversion potential ( ) equals the bulk potential. Note: dependent on N ot density and cutline depth. bulk potential ( B ) Inversion potential E f – E i (0) =
Extracting C ox and t ox Oxide Trapped Charge (10 12 cm -2 ) Cross over indicates TID susceptibility V T of “as drawn” V T of parasitic Slope C ox
Effective width (W eff. ) Parasitic nMOSFET width (W eff. ) is dependent on oxide charge, gate bias, and other parameters. N ot = 2x10 12 cm 2 V gs = 0.2V N ot = 5x10 12 cm 2 V gs = 0.2V N ot = 7x10 12 cm 2 V gs = 0.2V W (2) W (5) W (7)
Effective width (W eff. ) W eff BB ss W eff is calculated at a fixed gate bias and charge density over a specified depth (W o ).
Volumetric TID Simulations … use TCAD rad effects modeling to generate N OT as function of precursors, dose, dose rate, and electric field Sheet ChargeTrapped Charge vol. distribution How to relate device response to dose, process, and bias conditions …
New CMOS Processing Issues Retrograde Channel doping Non uniform doping profile used for modeling variation in channel doping. N S ~ (ITRS 2002) N B > (Brews TED 8-00) d = 25 nm (ITRS 2002) Strained silicon “Both [IBM and Intel] introduced strained silicon” in 90 nm. - Semiconductor Insights strained Si channel
Impact of Retrograde Without retrograde - wide channel - hi leakage Examine leakage channel inside box With retrograde - thin channel - lo leakage Will D-S leakage be a problem for 90 nm?