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Center for Power Electronics Systems A National Science Foundation Engineering Research Center Virginia Tech, University of Wisconsin - Madison, Rensselaer.

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Presentation on theme: "Center for Power Electronics Systems A National Science Foundation Engineering Research Center Virginia Tech, University of Wisconsin - Madison, Rensselaer."— Presentation transcript:

1 Center for Power Electronics Systems A National Science Foundation Engineering Research Center Virginia Tech, University of Wisconsin - Madison, Rensselaer Polytechnic Institute North Carolina A&T State University, University of Puerto Rico - Mayagüez SOFTWARE INTEGRATION USING STEP AP210 Prof. Jan Helge Bøhn Virginia Tech, Mechanical Engineering Blacksburg, Virginia 24061, USA Tel: , Fax: Mobile: NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA

2 1  CPES overview  Why software integration?  Sample demonstration case  Mini-consortium for AP210

3 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 2 CPES Overview  National Science Foundation (NSF) Engineering Research Center (ERC)  Five universities Virginia Tech, Univ. Wisconsin (Madison), RPI, NC A&T, Univ. Puerto Rico (Mayagüez)  85+ corporate members  $120M budget over 10 years (year 3)

4 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 3 CPES Vision  Improve the competitiveness of US power electronics industry by developing an integrated systems approach via Integrated Power Electronics Modules (IPEMs)  10 x improvement in quality, reliability, and cost effectiveness of power electronics systems

5 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 4 Why Software Integration? To achieve these goals, we must  push existing technologies to their limits and develop new ones as needed  use a multi-disciplinary set of software tools for design, modeling, and analysis, to optimize performance

6 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 5 Engineer Circuit Diagram Geometric Modeling Electrical Circuit Simulation Prototype Mechanical Layout FE Thermal Analysis FE EM Field Analysis FE Stress & Strain Analysis Cost Modeling Prototype 3D Solid-Body Modeling Geometry data Geometry data Prototype Engineer Electro- Dynamic Analysis FE Thermal Analysis FE EM Field Analysis FE Stress & Strain Analysis Cost Modeling The Multi-Disciplinary Analysis and Design Process Multi- Disciplinary Lumped Parameter Simulator Lumped Electrical Parameter Extractor Lumped Thermal Parameter Extractor Lumped Mechanical Parameter Extractor

7 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 6 The CPES Solution  STEP AP210 Since 1993: Rely on open international standards, and in particular

8 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 7 STEP Product Database Program Flow Control iSIGHT Cost Reliability (CALCE) Electro- Dynamic SABER Thermal FLOTHERM 3D Solid-Body I-DEAS Electro- Magnetic MAXWELL Mechanical ABAQUS Software Integration Platforms

9 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 8 Sample Demonstration Case  3D solid modeling  Electrical modeling and analysis  Thermal modeling and analysis  Automated optimization  Experimental verification Sample demonstration case to illustrate usefulness of integration of software tools for design, modeling, and analysis of an IPEM:

10 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 9 Integrated Electro-Mechanical Analysis DPSIPEM DesignAPEP Pre- regulator Power Factor Correction High Volt VRM On-board Converter On-board Low Volt VRM PCB IPEM V o LoLo P N O L 2 L 3 V in CoCo S1S1 S2S2 L1L1 Mechanical CAD  3D solid modeling  Electrical modeling and analysis  Thermal modeling and analysis  Automated optimization  Experimental verification 3D solid model (I-DEAS)

11 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 10 Power Device Copper (Top & Bottom) Solder Aluminum Oxide Heat Sink Thermal Grease What is the effect the parasitic capacitance? What is the effect the thermal resistance? Changing the Thickness of Al 2 O 3

12 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 11 First Generation Integration NOTES: Currently the heat sink thickness is provided as an explicit variable to Maxwell in addition to the geometry (which currently is transmitted only once in the form of an.STL file). Because Maxwell ignores the relative positioning of parts within an.STL file, these parts must be manually repositioned within Maxwell; hence, the geometry is only transferred once and the variable thickness is provided explicitly as it changes from one iteration to another. In the future, when using AP203/AP210, the entire geometry will, for each iteration, be transmitted to Maxwell without the need for manual repositioning of parts or the explicit information of heat sink thickness. I-DEAS (geometry) Maxwell Q3D Saber I-DEAS (thermal) Geometry Temperatures Parasitics: L, C Losses EMI Heat sink thickness Heat sink size External I-DEAS Design Variables see notes below iSIGHT flow control iSIGHT data storageSoftware Tools “Chicken & egg” iteration

13 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 12 Maxwell Result (L,C parasitics) IPEM equivalent circuit with DBC board parasitic parameters P N O Parasitic inductance matrix Parasitic capacitance matrix P_in 1N_out O_inN O_inP N_in O_out P_out IPEM model in MAXWELL O_inN O_inP N_in P_in O_inNO_inP N_inP_in (nH) O N P ONP(pF)

14 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 13 Saber Result (Losses, EMI) Saber circuit with LISN LISN Spectrum analysis of VR Output waveform O_out waveform IPEM

15 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 14 Using iSIGHT to change parameters & get results I-DEAS Geometry Maxwell Q3D Saber I-DEAS Thermal L, C iSIGHT Geometry Change Thickness Change Heat Sink Size Device Temperature Device Temperature EMI Temperature Distribution in IPEM and Heat Sink loss data and program program flow control flow control

16 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 15 I-DEAS Thermal & SABER Analysis Result Thickness (mm) Case 1: Heat Sink length 76 mmCase 2: Heat Sink length 30 mm After several iterations driven by iSIGHT, we can examine the tradeoff between EMI and device temperature. Current (A)Temp (°C) Current (A)

17 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 16 Motivation: Parasitic Inductance V o LoLo V in CoCo S1S1 S2S2 Voltage waveform of the bottom switch at turn off Voltage waveform of the bottom switch at turn off Ideal Case Non-ideal Case  To minimize the parasitic inductance, we want to place these two MOSFETs as close together as possible V o LoLo V in CoCo S1S1 S2S2

18 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 17 Motivation: Thermal Consideration Therefore  We need a 3D solid geometry based electrical and thermal model to address these issues  We need to integrated the electrical and thermal analysis tools to quantify these effects But if we place these two MOSFETs too close together, then the thermal interaction between them may cause the junction temperature to become too high

19 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 18 3D Solid Geometry Model  I-DEAS is a mechanical CAD tools that provides a strong mechanical modeling and analysis environment  The I-DEAS model of the IPEM contains all the necessary geometry and material information MOSFETP N O Wirebond 49mm 35mm I-DEAS Model of the IPEM

20 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 19 P N O Maxwell Q3D Model of the IPEM Maxwell Q3D Model (Parasitic Parameter Extraction) Parasitic Inductance  Maxwell Q3D Extractor uses the partial element equivalent circuit (PEEC) method to calculate the inductance from the geometry L2L2 L1L1 M 23 L3L3 M 12 M 13

21 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 20 Maxwell Q3D ExtractorSaber Model of the IPEM O N P S1 S2 P N O S1 Saber Model (losses, EMI)  In the Saber model, the equivalent inductance matrix obtained from Maxwell is encapsulated in one block

22 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 21 Experimental Verification P N O Maxwell Q3D Parameter Extractor Saber Simulation ResultWaveform Measurement Result Voltage waveform of the bottom switch at turn off

23 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 22 Thermal Modeling – FEA Method FLOTHERM Model of the IPEM The thermal analysis is based on:  Device power loss provided by Saber simulation  Geometry provided by I-DEAS  Boundary condition, such as air flow rate and ambient temperature Air flow FLOTHERM uses computational fluid dynamics (CFD) to predict air flow and heat transfer in and around the electronic systems

24 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 23 Thermal Modeling  The thermal resistance of the heat sink is much larger than that of any other package component  The size of the heat sink is determined by the device loss R j-hs R hs-a Power Devices Copper (top & bottom) Solder Aluminum Oxide Heat Sink Thermal Grease DBC <<

25 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 24 Comparison of Small and Large IPEM Geometry Case Study: Scaling down the size of the IPEM  Does not affect the parasitic inductance since both the length and width of the trace is reduced Large-Sized IPEMSmall-Sized IPEM L: 4~16nHL: 6~12nH

26 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 25 Comparison of Small and Large IPEM Geometry Case Study: Scaling down the size of the IPEM  Does not affect the power density since the size of heat sink is mainly determined by the power loss  T: 37  C  T: 40  C Large-Sized IPEMSmall-Sized IPEM

27 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 26 Example Conclusions  To minimize the parasitic inductance of the layout, we should keep the width of the copper trace as large as possible, but minimize the length of the trace.  Scaling down the size of the IPEM may not increase the high power density because the heat sink size is mainly determined by the power loss.

28 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 27 Future Work: What are the effect of layout on parasitic capacitance and EMI? P N O Parasitic capacitance matrix P N O IPEM model in MAXWELL Q3D Parasitic inductance matrix ONON OPOP N P ONON OPOP NP (nH) O N P ONP(pF) IPEM model in Saber Common-mode current spectrum

29 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 28 Future Work: How do we generalize the data and computational flow? NOTES: Currently the heat sink thickness is provided as an explicit variable to Maxwell in addition to the geometry (which currently is transmitted only once in the form of an.STL file). Because Maxwell ignores the relative positioning of parts within an.STL file, these parts must be manually repositioned within Maxwell; hence, the geometry is only transferred once and the variable thickness is provided explicitly as it changes from one iteration to another. In the future, when using AP203/AP210, the entire geometry will, for each iteration, be transmitted to Maxwell without the need for manual repositioning of parts or the explicit information of heat sink thickness. I-DEAS (geometry) Maxwell Q3D Saber I-DEAS (thermal) Geometry Temperatures Parasitics: L, C Losses EMI Heat sink thickness Heat sink size External I-DEAS Design Variables see notes below iSIGHT flow control iSIGHT data storageSoftware Tools “Chicken & egg” iteration

30 NASA's STEP for Aerospace Workshop January 17-19, 2001 JPL, Pasadena, CA 29 Acknowledgement This work was supported primary by the ERC Program of the National Science Foundation under Award Number EEC


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