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Published byJerome Hodgen Modified over 2 years ago

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**Modeling and Design for Beyond-the-Die Power Integrity**

Yiyu Shi, ECE Dept., Missouri Univ. of Science and Technology (formerly University of Missouri-Rolla) Lei He, EE Dept., Univ. of California, Los Angeles

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**Importance of Power Integrity**

Power supply noise is a major threat for circuit reliability in 45nm and beyond reduces noise margin of digital circuits shifts the operating point of analog circuits decreases the effective driving strength of the gates causes output signal distortion (e.g. jitters) impairing signal integrity

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**Simultaneous Switching Noise (SSN)**

a major threat to the power integrity occurs due to a very large amount of instantaneous P/G current from simultaneously switching gates mainly inductive most significantly observed around the output pads of the chip large I/O buffers clock synchronized I/O Large inductance in package

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**Power Delivery System three distinct peaks**

~kHz (power regulator/board) ~MHz (package/board) ~100MHz (chip/package) significant noise near the largest peak need accurate models to capture it Shi et al, “stochastic current prediction enabled frequency actuator for runtime resonance noise reduction”, ASPDAC’10 How to estimate SSN for a given design, and how to effectively suppress it?

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**Outline Chip Models Design Modeling Package and Board Models**

ECE902 VLSI Interconnect Modeling Chip Models Package and Board Models Design I/O planning and placement Decap Allocation Layer Stacking and P/G Plane Stapling Prepared by Lei He

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**Models for Chip/Package/Board**

impossible to put detailed models of chip, package and board together for the simulation due to the high complexity need some simplified models that preserve only necessary information for the simulation but how?

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**Transistor Models most accurate**

require detailed info about the circuit and process parameters, which vendors are reluctant to provide not all simulators are fully compatible slow simulation speed no convergence guarantee

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Current Source Model model the chip I/O as a time variant/invariant current source with parasitic R and C ↑ the non-linearity of the I/O buffer is ignored => negative feedback effect is ignored voltage drop ↓ switching current ↓

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**IBIS Models I/O Buffer Information Specification**

a universal standard for describing the buffers using data in ASCII text format Not really models just behavioral data to be used by simulators started in the early 90s to promote tool-independent I/O models for system-level signal integrity work IBIS 3.2 is standardized: ANSI/EIA-656-A and IEC IBIS 4.1 incorporates links to VHDL-AMS and Verilog-AMS IBIS Models Wiki: IBIS is a group of long-legged wading birds in the family Threskiornithidae

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**Elements of an IBIS Model**

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**Pros and Cons of IBIS Models**

simulate much faster than SPICE model protect circuit and process intellectual properties easy portability and guaranteed convergence Cons extrapolation required when load is out of the range (inaccurate) model regeneration required when the package parasitics change cannot capture the dynamic characteristics as the data relies primarily on static characteristics Only good when the I/O speed is not high!

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**Other Models for Chip I/O…**

use radial basis function (RBF) to represent the I/O dynamic behavior accurate intractable for complex driver circuits with multiple ports use spline functions with a finite time difference approximation include the previous time instances of the buffer output voltage/current cannot be extended to highly nonlinear buffers

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**Lumped/Distributed Models for Package/Board**

Lumped models use simple geometry with a few RLC elements (e.g. π equivalent circuit) efficient but lack accuracy should only be used for low performance/speed design Distributed models run parasitic extraction huge number of RLC elements model reduction or other simplification techniques are needed to reduce complexity High computational cost

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S-Parameters 101 measured by sending a single frequency signal into the network and detecting the exit waveform at each port frequency dependent, load dependent can be obtained using a 3D full-wave EM simulator such as HFSS or using vector network analyzer (VNA) By sweeping over a wide frequency range, they can reveal frequency-dependent characteristics (e.g. skin effect and dielectric conductance effect)

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**Simulation with S Parameters**

simulated directly using convolution-based methods in frequency domain or synthesize an RLC circuit from S-parameters in time domain create a circuit template with a certain topology convert the measured S parameters to Y or Z parameters matching the Y/Z parameters of the template and the measured Y/Z parameters to determine the element values in the template put some stringent requirements on S-parameters passivity (and thus stability and causality) but hard to satisfy while maintaining accuracy

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**Importance of Co-Simulation**

A differential pair from chip to package to board Comparison of the S11 parameter and the power supply voltage from chip, package and board co-simulation and these from separate simulation.

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**Possible Co-Simulation Flows**

Frequency domain Frequency model for circuit I/O Time domain IBIS model for circuit I/O S parameters for package/board Ckt realization of S parameters for package/board Inverse Transform

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**Outline Chip Models Design Modeling Package and Board Models**

ECE902 VLSI Interconnect Modeling Chip Models Package and Board Models Design I/O planning and placement Decap Allocation Layer Stacking and P/G Plane Stapling Prepared by Lei He

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**I/O Planning and Placement**

Flip-chip design Assign pins and pads to signals and power/ground supply Xiong et al, ““constraint driven I/O planning and placement for chip-package co-design”, ASPDAC’06

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Rule #1 separate the P/G pins and pads for analog and digital signals whenever possible minimize the digital noise coupled to the analog portion

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Rule #2 SSN is negatively correlated to the ratio of # of P/G pads/pins to # of signal pads/pins insert as many P/G pads and pins as possible total inductance ↓ (parallel connection) the slew of the SSN v.s. # of switching I/O buffers curve ↓ obtained from Q3D extraction

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**Decoupling Capacitor Allocation**

short power and ground planes at high frequencies to control voltage fluctuations discrete passive components with a given capacitance with parasitic resistance and inductance Determine the optimal decap allocation strategy

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Decap Allocation considering the congestion from signal and power routing, decaps can be inserted only at selected slots usually minimize the total decap cost subject to power integrity and congestion constraints Before decap allocation After decap allocation Hao et al, “Off-chip decoupling capacitor allocation for chip package co-design,” DAC’07 Chen et al, “Noise-driven in-package decoupling capacitance insertion,” ISPD’06

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**Layer Stacking and P/G Plane Stapling**

in high performance flip-chip package, multiple layers are typically used for P/G planes and signal routing Determine the number of layers and the locations of the vias to staple them

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**Determine the Number of Layers**

The # of layers depends on cost the # of the signals to be routed the cross-talk constraints of these signals the #of voltage domains, which constraints the # of power plane layers how a layer should be partitioned and shared by multiple voltage domains usually multiple P/G planes are used to keep the power supply noise low and to shield the signal routing layer If affordable, shield every routing layer by alternated power/ground planes in between

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**Stapling Rules the resonance frequency ↑ as the number of vias ↑**

the locations of the vias do not have a significant impact on the resonance frequency. Instead, they change the inductance of the package. a centered via distribution always has a lower inductance than a uniform via distribution Always cluster P/G vias for each power domain! centered uniform Zhao et al, “Effects of power/ground via distribution on the power/ground performance of C4/BGA packages,” epep’98.

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Conclusions Power integrity has become an increasingly important design consideration for circuit designs in 45nm technology and beyond We have provided an overview of power-integrity driven modeling and design issues for beyond the die We have discussed background of simultaneous switching noise (SSN) and its significance to the circuit designers various models of different accuracy and complexity for the board, package and chip different design techniques to suppress SSN

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