Presentation on theme: "Modeling and Design for Beyond-the-Die Power Integrity"— Presentation transcript:
1Modeling and Design for Beyond-the-Die Power Integrity Yiyu Shi, ECE Dept., Missouri Univ. of Science and Technology(formerly University of Missouri-Rolla)Lei He, EE Dept., Univ. of California, Los Angeles
2Importance of Power Integrity Power supply noise is a major threat for circuit reliability in 45nm and beyondreduces noise margin of digital circuitsshifts the operating point of analog circuitsdecreases the effective driving strength of the gatescauses output signal distortion (e.g. jitters) impairing signal integrity
3Simultaneous Switching Noise (SSN) a major threat to the power integrityoccurs due to a very large amount of instantaneous P/G current from simultaneously switching gatesmainly inductivemost significantly observed around the output pads of the chiplarge I/O buffersclock synchronized I/OLarge inductance in package
4Power Delivery System three distinct peaks ~kHz (power regulator/board)~MHz (package/board)~100MHz (chip/package)significant noise near the largest peakneed accurate models to capture itShi et al, “stochastic current prediction enabled frequency actuator for runtime resonance noise reduction”, ASPDAC’10How to estimate SSN for a given design, and how to effectively suppress it?
5Outline Chip Models Design Modeling Package and Board Models ECE902 VLSI InterconnectModelingChip ModelsPackage and Board ModelsDesignI/O planning and placementDecap AllocationLayer Stacking and P/G Plane StaplingPrepared by Lei He
6Models for Chip/Package/Board impossible to put detailed models of chip, package and board together for the simulation due to the high complexityneed some simplified models that preserve only necessary information for the simulationbut how?
7Transistor Models most accurate require detailed info about the circuit and process parameters, which vendors are reluctant to providenot all simulators are fully compatibleslow simulation speedno convergence guarantee
8Current Source Modelmodel the chip I/O as a time variant/invariant current source with parasitic R and C↑the non-linearity of the I/O buffer is ignored => negative feedback effect is ignoredvoltage drop ↓switching current ↓
9IBIS Models I/O Buffer Information Specification a universal standard for describing the buffers using data in ASCII text formatNot really modelsjust behavioral data to be used by simulatorsstarted in the early 90s to promote tool-independent I/O models for system-level signal integrity workIBIS 3.2 is standardized: ANSI/EIA-656-A and IECIBIS 4.1 incorporates links to VHDL-AMS and Verilog-AMSIBIS ModelsWiki: IBIS is a group of long-legged wading birds in the family Threskiornithidae
11Pros and Cons of IBIS Models simulate much faster than SPICE modelprotect circuit and process intellectual propertieseasy portability and guaranteed convergenceConsextrapolation required when load is out of the range (inaccurate)model regeneration required when the package parasitics changecannot capture the dynamic characteristics as the data relies primarily on static characteristicsOnly good when the I/O speed is not high!
12Other Models for Chip I/O… use radial basis function (RBF) to represent the I/O dynamic behavioraccurateintractable for complex driver circuits with multiple portsuse spline functions with a finite time difference approximationinclude the previous time instances of the buffer output voltage/currentcannot be extended to highly nonlinear buffers
13Lumped/Distributed Models for Package/Board Lumped modelsuse simple geometry with a few RLC elements (e.g. π equivalent circuit)efficient but lack accuracyshould only be used for low performance/speed designDistributed modelsrun parasitic extractionhuge number of RLC elementsmodel reduction or other simplification techniques are needed to reduce complexityHigh computational cost
14S-Parameters 101measured by sending a single frequency signal into the network and detecting the exit waveform at each portfrequency dependent, load dependentcan be obtained using a 3D full-wave EM simulator such as HFSS or using vector network analyzer (VNA)By sweeping over a wide frequency range, they can reveal frequency-dependent characteristics (e.g. skin effect and dielectric conductance effect)
15Simulation with S Parameters simulated directly using convolution-based methods in frequency domainor synthesize an RLC circuit from S-parameters in time domaincreate a circuit template with a certain topologyconvert the measured S parameters to Y or Z parametersmatching the Y/Z parameters of the template and the measured Y/Z parameters to determine the element values in the templateput some stringent requirements on S-parameterspassivity (and thus stability and causality)but hard to satisfy while maintaining accuracy
16Importance of Co-Simulation A differential pair from chip to package to boardComparison of the S11 parameter and the power supply voltage from chip, package and board co-simulation and these from separate simulation.
18Outline Chip Models Design Modeling Package and Board Models ECE902 VLSI InterconnectModelingChip ModelsPackage and Board ModelsDesignI/O planning and placementDecap AllocationLayer Stacking and P/G Plane StaplingPrepared by Lei He
19I/O Planning and Placement Flip-chip designAssign pins and pads to signals and power/ground supplyXiong et al, ““constraint driven I/O planning and placement for chip-package co-design”, ASPDAC’06
20Rule #1separate the P/G pins and pads for analog and digital signals whenever possibleminimize the digital noise coupled to the analog portion
21Rule #2SSN is negatively correlated to the ratio of # of P/G pads/pins to # of signal pads/pinsinsert as many P/G pads and pins as possibletotal inductance ↓ (parallel connection)the slew of the SSN v.s. # of switching I/O buffers curve ↓obtained from Q3D extraction
22Decoupling Capacitor Allocation short power and ground planes at high frequencies to control voltage fluctuationsdiscrete passive components with a given capacitance with parasitic resistance and inductanceDetermine the optimal decap allocation strategy
23Decap Allocationconsidering the congestion from signal and power routing, decaps can be inserted only at selected slotsusually minimize the total decap cost subject to power integrity and congestion constraintsBefore decap allocationAfter decap allocationHao et al, “Off-chip decoupling capacitor allocation for chip package co-design,” DAC’07Chen et al, “Noise-driven in-package decoupling capacitance insertion,” ISPD’06
24Layer Stacking and P/G Plane Stapling in high performance flip-chip package, multiple layers are typically used for P/G planes and signal routingDetermine the number of layers and the locations of the vias to staple them
25Determine the Number of Layers The # of layers depends oncostthe # of the signals to be routedthe cross-talk constraints of these signalsthe #of voltage domains, which constraintsthe # of power plane layershow a layer should be partitioned and shared by multiple voltage domainsusually multiple P/G planes are used to keep the power supply noise low and to shield the signal routing layerIf affordable, shield every routing layer by alternated power/ground planes in between
26Stapling Rules the resonance frequency ↑ as the number of vias ↑ the locations of the vias do not have a significant impact on the resonance frequency. Instead, they change the inductance of the package.a centered via distribution always has a lower inductance than a uniform via distribution Always cluster P/G vias for each power domain!centereduniformZhao et al, “Effects of power/ground via distribution on the power/ground performance of C4/BGA packages,” epep’98.
27ConclusionsPower integrity has become an increasingly important design consideration for circuit designs in 45nm technology and beyondWe have provided an overview of power-integrity driven modeling and design issues for beyond the dieWe have discussedbackground of simultaneous switching noise (SSN) and its significance to the circuit designersvarious models of different accuracy and complexity for the board, package and chipdifferent design techniques to suppress SSN