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Probabilistic Design Methodology to Improve Run- time Stability and Performance of STT-RAM Caches Xiuyuan Bi (1), Zhenyu Sun (1), Hai Li (1) and Wenqing.

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Presentation on theme: "Probabilistic Design Methodology to Improve Run- time Stability and Performance of STT-RAM Caches Xiuyuan Bi (1), Zhenyu Sun (1), Hai Li (1) and Wenqing."— Presentation transcript:

1 Probabilistic Design Methodology to Improve Run- time Stability and Performance of STT-RAM Caches Xiuyuan Bi (1), Zhenyu Sun (1), Hai Li (1) and Wenqing Wu (2) (1)University of Pittsburgh (2)Qualcomm Inc. 1

2 Introduction Spin-transfer torque random access memory (STT-RAM): Challenges: Write errors. In this work: – Reduce write errors. – Improve write performance. 2 STT-RAMSRAM Non-Volatility Low Leakage Cell Size Access Speed Endurance

3 Outline STT-RAM Basics Asymmetric Bit Error Rate Probabilistic Design Techniques – WRAP and VOW Hybrid STT-RAM Cache Hierarchy CONCLUSION 3

4 Free Layer Barrier Reference Layer STT-RAM Basics – Cell STT-RAM Cell: – Transistor and MTJ (Magnetic Tunnel Junction); MTJ: – Free Layer and Ref. Layer; – Read: Direction → Resistance; – Write: Current → Direction. 4 Parallel (R Low ), 0 Anti-Parallel (R High ), 1 Write-0 Write-1

5 STT-RAM Basics – Stochastic Switching Switching (writing) time of MTJ: – Random; Write errors: – Unsuccessful switching; To reduce error: – Longer write time; – Larger write current Switching time (ns)

6 Outline STT-RAM Basics Asymmetric Bit Error Rate Probabilistic Design Techniques – WRAP and VOW Hybrid STT-RAM Cache Hierarchy CONCLUSION 6

7 Asymmetric Bit Error Rate Write-1 vs. Write-0: With same write time: – Write-1 has higher bit error rate (BER) 7 MTJ Biasing Condition Biasing Condition Write-1 Harder Write-1 Harder

8 Asymmetric Bit Error Rate Temperature: Process Variations: – Larger impact on Write-1. 8 T T Current BER

9 Asymmetric Bit Error Rate Sub-Block: sub-BLock Error Rate (BLER): – Data pattern: – Strength of ECC: None < Hamming < BCH 9 64b ……64b Block (64 Byte) Sub-Block (64 bit) N 0→1 BLER

10 Outline STT-RAM Basics Asymmetric Bit Error Rate Probabilistic Design Techniques – WRAP and VOW Hybrid STT-RAM Cache Hierarchy CONCLUSION 10

11 Probabilistic Design How to reduce the write errors? Conventional Design: – Extend write time (Globally); – Use ECC; – Cons: High latency/energy. Still high error rate. Proposed probabilistic design: – WRAP and VOW – High performance, low energy, low write error rate. 11 Error Latency/energy Conv. Design Conv. Design Proposed Design Proposed Design

12 Probabilistic Design -- WRAP Write-verify-Rewrite with Adaptive Period (WRAP): Zero write error rate. Total latency: 12 Write Read Not Match Compare Done match

13 Probabilistic Design -- WRAP Optimal write pulse width τ opt exists. – τ opt affected by N 0->1 : Tracing N 0->1 is costly. – Using Hamming Weight to estimate N 0->1 13 Write Pulse (τ) BLER N iter

14 Probabilistic Design -- WRAP τ opt configuration: – Stored in look up table; – 0, 1, 2~8, 9~36, 37~64; – Temperature influence included; Circuit Diagram: 14

15 Probabilistic Design -- WRAP Performance overhead: – Selecting τ opt : No overhead. – Verify operation: Same location, only 1.47ns for each verify. High performance. 15

16 Probabilistic Design -- VOW For WRAP: – Verify stops the writes. Further improve performance: – Write & verify simultaneously. Major Challenge: – Total 4 possible voltages. – Frequently pre-charge. 16

17 Probabilistic Design -- VOW Solution: – Only verify write-1s. When Write-1s finishes: – BER0 extremely low. Verify One only: – Write-1s finish: stop; – Low sense complexity; – One-time precharge. 17

18 Probabilistic Design -- VOW Asymmetric Sense Amplifier (ASA): – Track the 0->1 switch; – Pre-charged to a sub-stable state; – Once switched to 1, OUT goes high. 18

19 Probabilistic Design -- Evaluation Baselines: – Other baseline: RWRV. Error Rate: 19

20 Probabilistic Design -- Evaluation Write Latency: Write Energy: 20

21 Probabilistic Design -- Evaluation Evaluation summary (vs. Hamming): – WRAP : Zero Write Error; 40% less latency. – VOW: Reduce error by ; 52% less latency (vs. Hamming). 21

22 Outline STT-RAM Basics Asymmetric Bit Error Rate Probabilistic Design Techniques – WRAP and VOW Hybrid STT-RAM Cache Hierarchy CONCLUSION 22

23 Hybrid Cache Hierarchy Using VOW as higher level cache: – Higher performance; – May contains errors, use parity check; WRAP as Lower level cache: – Provide golden copy. 23

24 Hybrid Cache Hierarchy Baselines: Base-B and Base-T: – Both use Hamming Code for write error protection; – Base-B : L2 write-back; – Base-T : L2 write-through. Evaluation Results: – Reduce write error rates by ; – Higher performance (6.8%), Lower energy cost (15%). 24

25 Outline STT-RAM Basics Asymmetric Bit Error Rate Probabilistic Design Techniques – WRAP and VOW Hybrid STT-RAM Cache Hierarchy CONCLUSION 25

26 Conclusion STT-RAM has random write errors; Write-1 has higher error rate than write-0; Two probabilistic design proposed to reduce write error while improve performance: – WRAP and VOW. A hybrid cache hierarchy is proposed to reduce error rate while improve system performance. 26

27 Thanks. Question? 27

28 backup

29 Hybrid Cache Hierarchy Write failure probability (WFP): Performance: 29

30 Hybrid Cache Hierarchy Energy: Evaluation Results: – Reduce write error rates by ; – Higher performance (6.8%) and Lower energy cost (15%). 30


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