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Advanced Digital Circuits ECET 146 Week 4 Professor Iskandar Hack ET 221B, 481-5733

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Presentation on theme: "Advanced Digital Circuits ECET 146 Week 4 Professor Iskandar Hack ET 221B, 481-5733"— Presentation transcript:

1 Advanced Digital Circuits ECET 146 Week 4 Professor Iskandar Hack ET 221B,

2 This Week’s Goals Introduction to VHDL Designing a Combinational Circuit from a Truth Table using a Case structure in VHDL Implementing a Truth Table in VHDL using a Case a Select structure

3 Design Example ABCDX

4 Introduction to VHDL VHSIC* Hardware Description Language (VHDL) is a way of describing the function of a digital circuit (in other words, describing what it does) in a text format. VHDL is, in part, an alternative to the traditional “schematic diagram” or logic diagram description of digital circuit functionality. VHDL is NOT a programming language!!! Programming languages are inherently sequential. One operation is executed, then the next, and the next, and so on. VHDL can and usually does include operations which execute concurrently or simultaneously, as do logic circuits.. *VHSIC is an acronym from the early 1980s. It stood for “Very High Speed Integrated Circuit”, but is hardly ever seen or heard nowadays. Others claimed it stood for Very Huge Sums of Infused Cash because of amount of money DOD spend on the development.

5 Introduction to VHDL VHDL may be written in such a way that VHDL code can be automatically translated into hardware by a process called logic synthesis. VHDL code which is written in such a way as to support logic synthesis is called synthesizable VHDL. Certain structures must be avoided if code is intended to be synthesizable. For example, the statement “a = a + 1”, which is a common structure in software languages, must be avoided in VHDL if it is to be synthesizable. Non-synthesizable code is supported, and is used for things like test benches.

6 Some Simple VHDL Code: First, a couple of formalities. The VHDL source file has to begin with a library clause, listing the libraries which are to be used. This is normally followed by one or more use clauses, which identify the specific library units to be used from the libraries listed in the library clause For our example, which will implement a truth table, the library clause and use clauses look like this:

7 Some Simple VHDL Code Notice that each of these two lines ends with a semicolon. Most lines of code end with semicolons. The most common coding error is omission of the semicolon at the end of a line of code. The next thing to add is one or more enitity declarations. An entity is a black box, with inputs and outputs. Inputs and outputs are defined as ports. The entity declaration says nothing about what the entity does.

8 Some Simple VHDL Code You may visualize our entity, a four-input, one-output combinatorial logic block implementing a truth table, like this: A(3) A(2) A(1) A(0) D TruthTable The four inputs are shown as four bits of a four-bit input vector A. A(3) is the most-significant bit (MSB), A(0) is the least- significant bit (LSB).

9 Some Simple VHDL Code After adding the entity declaration, our source file looks like this: Notice how the Port statement is indented, and how a blank line is left between the use clause and the entity declaration. These are examples of coding style, which is used to make code more readable. It is good practice, and is often required by an employer, customer or client. We still haven’t defined what the entity actually does. That comes next, in the architecture body.

10 Some Simple VHDL Code The simplest architecture just implements a with/select command that resembles the Table Command in AHDL : The line following the “BEGIN” is an assignment statement. There is a output of ‘1’ for each line of the truth table which contains a ‘1’ in the X column and ‘0’ for others.

11 Some Simple VHDL Code A(3)A(2)A(1)A(0)XProduct Term (NOT A(3) AND NOT A(2) AND A(1) AND NOT A(0)) 00111(NOT A(3) AND NOT A(2) AND A(1) AND A(0)) 01001(NOT A(3) AND A(2) AND NOT A(1) AND NOT A(0)) (NOT A(3) AND A(2) AND A(1) AND A(0)) 10001(A(3) AND NOT A(2) AND NOT A(1) AND NOT A(0)) (A(3) AND NOT A(2) AND A(1) AND A(0)) 11001(A(3) AND A(2) AND NOT A(1) AND NOT A(0)) (A(3) AND A(2) AND A(1) AND NOT A(0)) 11110

12 Some Simple VHDL Code Here’s the entire VHDL source file:

13 Some Simple VHDL Code Start Quartus II. Select File -> New, and create a new VHDL file. Name it TruthTable.vhd, and save it in a folder named “TruthTable” on your flash drive. Enter the source code shown in the previous slide in the file you just created, and save it. Select File -> New Project Wizard, then click the “Next” button.

14 Some Simple VHDL Code Click the “…” next to “What is the working directory for this project”, then navigate to the “TruthTable” folder you created. Click OK on the file selection dialog. The path of the TruthTable folder should appear as shown here.

15 Some Simple VHDL Code Click the “…” next to “What is the name of this project”, then select “TruthTable.vhd” on the file selection dialog and click OK.

16 Some Simple VHDL Code “TruthTable” should appear as the project name and as the top-leel design entity. Click the “Finish” button.

17 Some Simple VHDL Code Next, open your project by selecting File-> Open Project. Navigate to your TruthTable folder, select the file TruthTable.qpf, and click the “open” button. Add your source file, “TruthTable.vhd”, to the project by slecting Project->Add/Remove Files in Project. Click the “…” button on the “settings” dialog, then navigate to the project folder and select TruthTable.vhd. Click the “open” button on the file selection dialog, then click the “Add” button on the “settings” dialog. Click the “OK” button on the settings dialog to dismiss the dialog.

18 Some Simple VHDL Code In the Quartus II Project Navigator pane, select the “Files” tab as shown below.

19 Some Simple VHDL Code Expand the “Device Design Files” folder by clicking the “+” beside it: You should see your VHDL source file. Click on it.

20 Some Simple VHDL Code Click the “start compilation button:

21 Some Simple VHDL Code If you haven’t made any typing errors (like leaving out semicolons), your code should compile successfully. It could take several minutes. If the compiler finds any errors, correct them and try again.

22 Some Simple VHDL Code Now, create a waveform file to provide the inputs to the design. You’ve done this in the previous lab, but here are the instructions again. Select File->New. When the dialog appears, choose the “Other Files tab:

23 Some Simple VHDL Code Select “Vector Waveform File”, and click the OK button to dismiss the dialog.

24 Some Simple VHDL Code When the resulting vector waveform file, probably with the default name “Waveform1.vwf”, appears, select File->Save As and save it as “TruthTable.vwf”.

25 Some Simple VHDL Code Right-click in the blank space under “Name”, and select “Insert->Insert Node or Bus”

26 Some Simple VHDL Code Right-click in the blank space under “Name”, and select “Insert->Insert Node or Bus”

27 Some Simple VHDL Code Click the “Node Finder” button …

28 Some Simple VHDL Code The Node Finder dialog appears. Make sure the Name box contains a “*” (asterisk) and the “Filter” box contains “Pins: all” as shown, then click the List button.

29 Some Simple VHDL Code The Node Finder dialog appears. Make sure the Name box contains a “*” (asterisk) and the “Filter” box contains “Pins: all” as shown, then click the List button.

30 Some Simple VHDL Code The vector A appears under Nodes Found, as do each of its individual bits and the output X. Select A, and click the “>” button:

31 Some Simple VHDL Code A appears under selected nodes. Select X, and click the “>” again:

32 Some Simple VHDL Code You have selected all the inputs and outputs for this simple design. Click “OK” to dismiss the node finder.

33 Some Simple VHDL Code You have selected all the inputs and outputs for this simple design. Click “OK” to dismiss the node finder.

34 Some Simple VHDL Code Click “OK” to dismiss the “Insert Node or Bus” dialog.

35 Some Simple VHDL Code A and X appear on the waveform editor.

36 Some Simple VHDL Code Left-Click on A to select it, then click the “count value” button:

37 Some Simple VHDL Code Left-Click on A to select it, then click the “count value” button:

38 Some Simple VHDL Code On the Count Value dialog, select the Timing tab …

39 Some Simple VHDL Code Make sure the Start Time is 0 and the End time is 1 microsecond. Make sure “At Absolute Times” is selected, and the “Count Every” value is 50 ns (nanoseconds). Click “OK”:

40 Some Simple VHDL Code Notice that the value of A is now a hexidecimal number which increments every 50 nS until it reaches “F”, then starts over from 0. Xout is unknown, because we haven’t run the simulator yet.

41 Some Simple VHDL Code Select Processing->Simulator Tool Make sure TruthTable.vwf is selected as the “Simulation Input”, then click the “Start Simulation” button:

42 Some Simple VHDL Code If the simulator fails, correct any errors in your code and try again. If the simulation is successful, scroll to the bottom of the simulator tool dialog and click the “Report” button.

43 Some Simple VHDL Code Examine the waveforms, and decide whether you have successfully implemented the truth table. You may expand A to examine the individual bits by clicking on the “+”

44 Some Simple VHDL Code Examine the waveforms, and decide whether you have successfully implemented the truth table. You may expand A to examine the individual bits by clicking on the “+”

45 Open the Programming Module Select the Programmer Hot Button

46 Select Programming Hardware Once the programmer is opened – hit hardware setup Then select Add Hardware Selected Byteblaster on LPT1:

47 Select Programming Options Select Program/Configure and Verify

48 Program the Part Hit the start button You should see the progress bar move during programming. Note the run/prog switch must in the RUN postition

49 Verify the Design Using the switches SW0-SW3, and LEDR0 verify your truth table

50 Summary This week we covered how to design a circuit without drawing ANY schematics using the waveform editor We also got our first look at designing a circuit by using VHDL (also without drawing schematics) We also we reviewed how to verify a combinational logic design using the Altera hardware

51 Lab Three Design a circuit and verify it using the techniques (first using waveform design and again using VHDL) covered in this week’s lecture that will have the following truth table. Turn in your printouts from source code and simulator. Download only the project from VHDL to the board and verify it’s operation in hardware ABCDX


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