Presentation on theme: "Adam Sarhage. Current CMOS technology is reaching its theoretical limits for operating speed, and the next generation of supercomputers could require."— Presentation transcript:
Current CMOS technology is reaching its theoretical limits for operating speed, and the next generation of supercomputers could require hundreds of megawatts of power to operate if based on CMOS technology. Superconducting logic, which uses zero- resistance superconductors, could provide the basis for future supercomputers using 1/300 th of the power required by a comparable CMOS supercomputer.
Comprised of a non-superconducting material or insulating material sandwiched between two superconducting materials Superconducting electronics are able to pass though without resistance until the critical current is reached Superconducting Material Insulating Material I-V Curve Schematic Symbol
Using the properties of the Josephson junction, circuits can be built which pass individual flux quanta (a quantum being the smallest amount of magnetic flux) through an IC.
Traditionally, as is the case with Rapid Single Flux Quantum (RSFQ) technology, the transmission lines are biased using DC current. This DC current requires a resistor dissipating power at each point set of Josephson Junctions on the JTL. As the technology scales up, a substantial and prohibitive amount of power is dissipated in the DC biasing resistors.
A new technology, Reciprocal Quantum Logic (RQL) seeks to eliminate the DC biasing resistors by providing the biasing current through a transformer coupled AC bias/clock line.
Logical bits are stored in the phase of the flux quanta. A logical “1” is a produced by a flux quantum’s phase shift of +2π during the positive half of the clock cycle followed by a phase shift of -2π during the immediately proceeding negative half of the clock cycle. A logical “0” is produced by not changing the phase of a flux quantum during the clock cycle.
RQL requires a JTL buffer between the output of a logic gate and the input of another logic gate. A finite number of logic gates and buffers can be placed on a single phase of the clock. With a 20GHz clock, approximately 4 gates/buffers can be on the same clock phase.
Gates/buffers can only be connected to their own clock phase or the next highest clock phase. (e.g. A phase 00 buffer can only be connected to a phase 00 or phase 01 buffer, not a phase 10 or 11 buffer.) This makes synthesis using VHDL unique and challenging.
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