Presentation on theme: "May 3, 2015204521 Digital System Architecture Technology Trends Pradondet Nilagupta Fall 2005 (original notes from Randy Katz, & Prof. Jan M. Rabaey, UC."— Presentation transcript:
May 3, Digital System Architecture Technology Trends Pradondet Nilagupta Fall 2005 (original notes from Randy Katz, & Prof. Jan M. Rabaey, UC Berkeley)
May 3, Digital System Architecture2 Original Big Fishes Eating Little Fishes
May 3, Digital System Architecture Computer Food Chain PCWork- station Mini- computer Mainframe Mini- supercomputer Supercomputer Massively Parallel Processors
May 3, Digital System Architecture Computer Food Chain Mini- supercomputer Massively Parallel Processors Mini- computer PCWork- station Mainframe Supercomputer Now who is eating whom? Server
May 3, Digital System Architecture Computer Food Chain Technologies PCWork- station Mini- computer Mainframe Mini- supercomputer Supercomputer ECLTTL MOS
May 3, Digital System Architecture6 Why Such Change in 10 years? (1/2) Function –Rise of networking/local interconnection technology Performance –Technology Advances CMOS VLSI dominates TTL, ECL in cost & performance –Computer architecture advances improves low-end RISC, Superscalar, RAID, …
May 3, Digital System Architecture7 Why Such Change in 10 years? (2/2) Price: Lower costs due to … –Simpler development CMOS VLSI: smaller systems, fewer components –Higher volumes CMOS VLSI : same dev. cost 10,000 vs. 10,000,000 units –Lower margins by class of computer, due to fewer services
May 3, Digital System Architecture8 Technology Trends: Microprocessor Capacity Moore ’ s Law CMOS improvements: Die size: 2X every 3 yrs Line width: halve / 7 yrs “ Graduation Window ” Alpha 21264: 15 million Pentium Pro: 5.5 million PowerPC 620: 6.9 million Alpha 21164: 9.3 million Sparc Ultra: 5.2 million
May 3, Digital System Architecture9 Memory Capacity (Single Chip DRAM) year size(Mb)cyc time ns ns ns ns ns ns ns
May 3, Digital System Architecture10 CMOS Improvements Die size 2X every 3 yrs Line widths halve every 7 yrs Die Size Line Width Improvement Die size increase plus transistor count increase Transistor Count
May 3, Digital System Architecture11 Memory Size of Various Systems Over Time 128K 128M K 1M 8M 1G 8G chip 1Kbit 640K 4K16K64K256K1M4M16M64M 256M DOS limit 1/8 chip 8 chips-PC 64 chips workstation 512 chips 4K chips Bytes Time
May 3, Digital System Architecture12 Technology Trends (Summary) CapacitySpeed (latency) Logic2x in 3 years2x in 3 years DRAM4x in 3 years2x in 10 years Disk4x in 3 years2x in 10 years
May 3, Digital System Architecture13 Processor Frequency Trend Ê Frequency doubles each generation Ë Number of gates/clock reduce by 25% Ê Frequency doubles each generation Ë Number of gates/clock reduce by 25%
May 3, Digital System Architecture14 Processor Performance Trends
May 3, Digital System Architecture15 Performance vs. Time Mips 25 MHz Performance (VAX 780s) MV10K 68K MHz RISC 60% / yr. uVAX 6K (CMOS) 8600 TTL ECL 15%/yr. CMOS CISC 38%/yr. o | | MIPS (8 MHz) o 9000 Mips (65 MHz) uVAX CMOS Will RISC continue on a 60%, (x4 / 3 years)? 4K
May 3, Digital System Architecture16 Processor Performance (1.35X before, 1.55X now) 1.54X/yr
May 3, Digital System Architecture17 Summary: Performance Trends Workstation performance (measured in Spec Marks) improves roughly 50% per year (2X every 18 months) Improvement in cost performance estimated at 70% per year
May 3, Digital System Architecture18 Processor Perspective Putting performance growth in perspective: IBM POWER2 Cray YMP Workstation Supercomputer Year MIPS> 200 MIPS< 50 MIPS Linpack140 MFLOPS160 MFLOPS Cost$120,000$1M ($1.6M in 1994$) Clock71.5 MHz167 MHz Cache256 KB0.25 KB Memory512 MB256 MB 1988 supercomputer in 1993 server!
May 3, Digital System Architecture19 Where Has This Performance Improvement Come From? Technology? Organization? Instruction Set Architecture? Software? Some combination of all of the above?
May 3, Digital System Architecture20 Performance Trends Revisited (Architectural Innovation) Microprocessors Minicomputers Mainframes Supercomputers Year CISC/RISC
May 3, Digital System Architecture21 Performance Trends Revisited (Microprocessor Organization) Bit Level Parallelism Pipelining Caches Instruction Level Parallelism Out-of-order Xeq Speculation...
May 3, Digital System Architecture22 What is Ahead? Greater instruction level parallelism? Bigger caches? Multiple processors per chip? Complete systems on a chip? (Portable Systems) High performance LAN, Interface, and Interconnect
May 3, Digital System Architecture23 Hardware Technology Memory chips64 K 4 M 256 M-1 G Speed /4 in. disks40 M 1 G 20 G Floppies.256 M 1.5 M 500-2,000 M LAN (Switch)2-10 Mbits 10 (100) (ATM) Busses2-20 Mbytes
May 3, Digital System Architecture24 Software Technology Languages C, FORTRAN C++, HPF object stuff?? Op. System proprietary +DUM* +DUM+NT User I/F glass Teletype WIMP* stylus, voice, audio,video, ?? Comp. Styles T/S, PC Client/Server agents*mobile New things PC & WS parallel proc. appliances Capabilities WP, SS WP,SS, mail video, ?? DUM = DO S, n-UNIX's, MAC WIMP = Windows, Icons, Mouse, Pull-down menus Agents = robots that work on information
May 3, Digital System Architecture25 Computer Technology Trends: Evolutionary but Rapid Change Processor: – performance improvement every year; Over 100X performance in last decade. Memory: –DRAM capacity: > 2x every 1.5 years; 1000X size in last decade. –Cost per bit: Improves about 25% per year. Disk: –Capacity: > 2X in size every 1.5 years. –Cost per bit: Improves about 60% per year. –200X size in last decade. –Only 10% performance improvement per year, due to mechanical limitations. Expected State-of-the-art PC by end of year 2005 : –Processor clock speed: > 4000 MegaHertz (4 Giga Hertz) –Memory capacity: > 4000 MegaByte (4 Giga Bytes) –Disk capacity:> 500 GigaBytes (0.5 Tera Bytes)
May 3, Digital System Architecture26 Recent Architectural Improvements Increased optimization and utilization of cache systems. Memory-latency hiding techniques. Optimization of pipelined instruction execution. Dynamic hardware-based pipeline scheduling. Improved handling of pipeline hazards. Improved hardware branch prediction techniques. Exploiting Instruction-Level Parallelism (ILP) in terms of multiple-instruction issue and multiple hardware functional units. Inclusion of special instructions to handle multimedia applications (limited vector processing). High-speed bus designs to improve data transfer rates.
May 3, Digital System Architecture27 Applications: Unlimited Opportunities (1/2) Office agents: phone/FAX/comm; files/paper handling Untethered computing: fully distributed offices ?? Integration of video, communication, and computing: desktop video publishing, conferencing, & mail Large, commercial transaction processing systems Encapsulate knowledge in a computer: scientific & engineering simulation (e.g.. planetarium, wind tunnel,... )
May 3, Digital System Architecture28 Applications: Unlimited Opportunities (2/2) Visualization & virtual reality Computational chemistry e.g. biochemistry and materials Mechanical engineering without prototypes Image/signal processing: medicine, maps, surveillance. Personal computers in 2001 are today's supercomputers Integration of the PC & TV => TC
May 3, Digital System Architecture29 Challenges for 1990s Platforms (1/2) 64-bit computers video, voice, communication, any really new apps? Increasingly large, complex systems and environments Usability? Plethora of non-portable, distributed, incompatible, non-interoperable computers: Usability? Scalable parallel computers can provide “commodity supercomputing”: Markets and trained users?
May 3, Digital System Architecture30 Challenges for 1990s Platforms (2/2) Apps to fuel and support a chubby industry: communications, paper/office, and digital video The true portable, wireless communication computer Truly personal card, pencil, pocket, wallet computer Networks continue to limit: WAN, ISDN, and ATM?