# L31: Partitioning(2) 성균관대학교 조 준 동 교수

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L31: Partitioning(2) 성균관대학교 조 준 동 교수 http://vlsicad.skku.ac.kr

Multilevel Kernighan-Lin Gc is computed in step (1) of Recursive_partition as follows. We define a matching of a graph G=(N,E) as a subset Em of the edges. E with the property that no two edges in Em share an endpoint. A maximal matching is one to which no more edges can be added and remain a matching. We can compute a maximal matching by a simple random algorithm: let Em be empty mark all nodes in N as unmatched for i = 1 to |N|... visit the nodes in a random order if node i has not been matched, choose an edge e=(i,j) where j is also unmatched, and add it to Em mark i and j as matched end if end for Given a matching, Gc is computed as follows. We let there be a node r in Nc for each edge in Em. Then we construct Ec as follows: for r = 1 to |Em|... for each node in Nc let (i,j) be the edge in Em corresponding to node r for each other edge e=(i,k) in E incident on i let ek be the edge in Em incident on k, and let rk be the corresponding node in Nc add the edge (r,rk) to Ec end for for each other edge e=(j,k) in E incident on j let ek be the edge in Em incident on k, and let rk be the corresponding node in Nc add the edge (r,rk) to Ec end for if there are multiple edges between pairs of nodes of Nc, collapse them into single edges

Multilevel Kernighan-Lin Note that we can take node weights into account by letting the weight of a node (i,j) in Nc be the sum of the weights of the nodes I and j. We can similarly take edge weights into account by letting the weight of an edge in Ec be the sum of the weights of the edges "collapsed" into it. Furthermore, we can choose the edge (i,j) which matches j to i in the construction of Nc above to have the large weight of all edges incident on i; this will tend to minimize the weights of the cut edges. This is called heavy edge matching in METIS, and is illustrated on the right.

Multilevel Kernighan-Lin Given a partition (Nc+,Nc-) from step (2) of Recursive_partition, it is easily expanded to a partition (N+,N-) in step (3) by associating with each node in Nc+ or Nc- the nodes of N that comprise it. This is again shown below: Finally, in step (4) of Recurive_partition, the approximate partition from step (3) is improved using a variation of Kernighan-Lin.

Multilevel Spectral Partitioning There is a simple "greedy" algorithm for finding an Nc: Nc = empty set for i = 1 to |N| if node i is not adjacent to any node already in Nc add i to Nc end if end for This is shown below in the case where G is simply a chain of 9 nodes with nearest neighbor connections, in which case Nc consists simply of every other node of N. Now we turn to the divide-and-conquer algorithm of Barnard and Simon, which is based on spectral partitioning rather than Kernighan-Lin. The expensive part of spectral bisection is finding the eigenvector v2, which requires a possibly large number of matrix-vector multiplications with the Laplacian matrix L(G) of the graph G. The divide-and-conquer approach of Recursive_partition will dramatically decrease the cost. Barnard and Simon perform step (1) of Recursive_partition, computing Gc = (Nc,Ec) from G=(N,E), slightly differently than above: They find a maximal independent subset Nc of N. This means that N contains Nc and E contains Ec, no nodes in Nc are directly connected by edges in E (independence), and Nc is as large as possible (maximality).

hMETIS hMETIS is a set of programs for partitioning hypergraphs such as those corresponding to VLSI circuits. The algorithms implemented by hMETIS are based on the multilevel hypergraph partitioning scheme described in [KAKS97]. hMETIS produces bisections that cut 10% to 300% fewer hyperedges than those cut by other popular algorithms such as PARABOLI, PROP, and CLIP- PROP, especially for circuits with over 100,000 cells, and circuits with non- unit cell areaIt is extremely fast!A single run of hMETIS is faster than a single run of simpler schemes such as FM, KL, or CLIP. Furthermore, because of its very good average cut characteristics, it produces high quality partitionings in significantly fewer runs. It can bisect circuits with over 100,000 vertices in a couple of minutes on Pentium-class workstations. The performance of hMETIS on the new ISPD98 benchmark suite can be found in the paper by Chuck Alpert. =http://www.users.cs.umn.edu/~karypis/metis/metis.html

How good is Recursive Bisection ? Horst D. Simon and Shang-Hua Teng, Report RNR-93-012, August 1993 The most commonly used p-way partitioning method is recursive bisection. It first "optimally" divides the graph (mesh) into two equal sized pieces and then recursively divides the two pieces.We show that,due to the greedy nature and the lack of global information,recursive bisection, in the worst case,may produce a partition that is very far from the optimal one. Our negative result is complemented by two positive ones.First, we show that for some important classes of graphs that occur in practical applications,such as well shaped finite element and finite difference meshes,recursive bisection is normally within a constant factor of the optimal one. Secondly,we show that if the balanced condition is relaxed so that each block in the partition is bounded by (1+e)n/p,then there exists a approximately balanced recursive partitioning scheme that finds a partition whose cost is within an 0(log p) factor of the cost of the optimal p-way partition.

Partitioning Algorithm with Multiple Constraints 1998. 5. 19 조 준 동

스위칭에 의한 충전과 방전 전체 전력소모의 최대 90% 까지 차지

저전력을 위한 분할 기존의 방법 : cut 을 지나가는 간선의 수 저전력 : 간선의 스위칭 동작의 수

최소비용흐름 알고리즘 주어진 양을 가장 적은 비용으로 원하는 목적지까지 보낼수 있는 방법 – 각 통로는 용량과 비용을 가짐 Max-flow min-cut : 간선의 수만 고려 Min-Cost flow : 간선마다 스위칭 동작의 가중치를 부여 – 비용 : 스위칭 동작 vs. 간선의 수 – 용량 : 간선에 흐를 수 있는 최대양 비용이 적을수록 선택되도록 큰 용량

Network and Mincost Flow

그래프 변환 알고리즘 Min-Cost Flow 경로를 찾음 Cut 을 찾기 위해서 그래프의 변환이 필요 레벨에 따른 topological 정렬

그래프 변환 알고리즘 추가된 노드 및 간선

그래프 변환

Partitioning with constraints

Algorithm Input: Flow f, Network Output: Partition the network into f subnetworks 단계 1: 그래프에 Flow 를 push 하여 최소비용흐름 알고리즘 수행 ; 만약 각각의 partition 에 대하여 A_upper 또는 P_upper 를 만족하면 마침 ; 그렇지않으면 f = f+1; 증가시키고 upper bound 를 만족할 때까지 단계 1 을 반복한다. 단계 2: 만약 A_lower 또는 P_lower 를 만족하지 않는두개의 partition p, q 가 있고 라면 p 와 q 는 merge 가 가능하고 모든 가능한 {p,q} set 에 대하여 최소비용매칭을 적용 하여 분할된 partition 의 개수를 줄임.

참고문헌 [1] J.D.Cho and P.D.Franzon, "High-Performance Design Automation for Multi-Chip Modules and Packages", World Scientific Pub. Co. 1996 [2] H.J.M.Veendrick, "Short-Circuit Dessipation of Static CMOS Circuitry and its Impact on the Design of Buffer Circuits" IEEE JSSCC, pp.468-473, August, 1984 [3] H.B.Bakoglu, "Circuits, Interconnections and Packaging for VLSI", pp.81-112, Addison-Wesley Publishing Co., 1990 [4] K.M.hall. "An r-dimensional quadratic placement algorithm", Management Sci., vol.17, pp.219-229, Nov, 1970 [5] Cadence Design Systems. "A Vision for Multi-Chip Module design in the nineties", Tech. Rep. Cadence Design Systems Inc., Santa Clara, CA, 1993 [6] R.Raghavan, J.Cohoon, and S.Shani. "Single Bend Wiring", Journal of Algorithms, 7(2):232-257, June, 1986 [7] Kernighan, B.W. and S.lin. "An efficient heuristic procedure to partition graphs" Bell System Technical Journal, 492:291-307, Feb. 1970 [8] Wei, Y.C. and C.K.Cheng "Ratio-Cut Partitioning for Hierachical Designs", IEEE Trans. on Computer- Aided Design. 40(7):911-921, 1991 [9] S.W.Hadley, B.L.Mark, and A.Vanelli, "An Efficient Eigenvector Approach for Finding Netlist Partitions", IEEE Trans. on Computer-Aided Design, vol. CAD-11, pp.85-892, July, 1992 [10] L.R.Fold, Jr. and D.R.Fulkerson. "Flows in Networks", Princeton University Press, Princeton, NJ, 1962 [11] Liu H. and D.F.Wong, "Network Flow Based Multi-Way Partitioning With Area and Pin Constraints", IEEE/ACM Symposium on Physical Design, pp. 12-17, 1997 [12] Kirkpatrick, S. Jr., C.Gelatt, and M.Vecchi. "Optimization by simulated annealing", Science, 220(4598):498-516, May, 1983 [13] Pedram, M. "Power Minimization in IC Design: Principles and Applications," ACM Trans. on Design Automation of Electronics Systems, 1(1), Jan. pp. 3-56, 1996. [14] A.H.Farrahi and M.Sarrafzadeh. "FPGA Technology Mapping for Power Minimizatioin", In International Workshop on Field-Programmable Logic and Applications, pp66-77, Sep. 1994 [15] M.A.Breur, "Min-Cut Placement", J.Design Automation and Fault-Tolerant Computing, pp.343-382, Oct. 1977

[16] M.Hanan and M.J.Kutrzberg. A Review of the Placement and the Quadratic Assignment Problem, Apr. 1072. [17] N.R.Quinn, "The Placement Problem as Viewed from the Physics of Classical Mechanics", Proc. of the 12th Design Automation Conference, pp.173-178, 1975 [18] C.Sehen, and A.Sangiovanni-Vincentelli, "The Timber Wolf placement and routing package", IEEE Journal of Solid-State Circuits, Sc-20, pp.501-522, 1985 [19] K.Shahookar, and P.Mazumder, "A Genetic Approach to Standard Cell Placement", First European Design Automation Conference, Mar. 1990 [20] J.D.Cho, S.Raje, M.Sarrafzadeh, M.Sriram, and S.M.Kang, "Crosstalk Minimum Layer Assignment", In Proc. IEEE Custom Integr. Circuits Conf., San Diego, CA, pp.29.7.1-29.7.4, 1993 [21] J.M.Ho, M.Sarrafzadeh, G,Vijayan, and C.K.Wong. "Layer Assignment for Multi-Chip Modules", IEEE Trans. on Computer-Aided Design, CAD-9(12):1272-1277, Dec., 1991 [22] G.Devaraj. "Distributed placement and crosstalk driven router for multichip modules", In MS Thesis, Univ. of Cincinnati, 1994 [23] J.D.Cho. "Min-Cost Flow based Minimum-Cost Rectilinear Steiner Distance-Preserving Tree", International Symposium on Physical Desigh, pp-82-87, 1997 [24] A.Vitttal and M.Marek-Sadowska. "Minimal Delay Interconnection Design using Alphabetic Trees", In Design Automation Conference, pp.392-396, 1994 [25] M.C.Golumbic. "Algorithmic Graph Theory and Perfect Graph", pp.80-103, New York : Academic. 1980 [26] R.Vemuri. "Genetic Algorithms for partitioning, placement, and layer assignment for multichip modules", Ph.D. Thesis, Univ. of Cincinnati, 1994 [27] J.L.Kennington and R.V.Helgason, "Algorithms for Network Programmin", John Wiley, 1980 [28] J.Y.Cho and J.D.Cho "Improving Performance and Routability Estimation in MCM Placement", In InterPack'97, Hawaii, June, 1997 [29] J.Y.Cho and J.D.Cho "Partitioning for Low Power Using Min-Cost Flow Algorithm", submitted to 한국반도체학술대회, Feb, 1998

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