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The VLSI Systems Center - BGU AMS – Test Manual by Slava Fleshel 309284222.

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Presentation on theme: "The VLSI Systems Center - BGU AMS – Test Manual by Slava Fleshel 309284222."— Presentation transcript:

1 The VLSI Systems Center - BGU AMS – Test Manual by Slava Fleshel

2 The VLSI Systems Center - BGU Topics  Cautions Cautions I.Getting StartedGetting Started II.Start building the TestStart building the Test III.Open “Analog environment” Open “Analog environment”Open “Analog environment” IV.Setting Analog EnvironmentSetting Analog Environment V.Run the SimulationRun the Simulation VI.Failures & SolutionsFailures & Solutions

3 The VLSI Systems Center - BGU CAUTIONS lowercase  In the design, cell names, net names except primitive cells should be ALL lowercase (minuscule)!! escaped  Also it should not contain the “escaped” characters (+,=,-,&…)!!  If you have big design, do not save all nets on all hierarchies it can cause a serious problems, and the simulation would not run!!

4 The VLSI Systems Center - BGU Getting Started I.First you should check that all directories you need for the test and have cell’s in them are written in the “Library Path Editor”, a spatially you shouldn’t forget the directory of “Connect rules” if needed. In fig’ 1 shown the example of how can “Library Path Editor” look.

5 The VLSI Systems Center - BGU Figure 1 :

6 The VLSI Systems Center - BGU II.Now you can start building the Test. a.Create “schematic view” of the cell you want to simulate and create in it your test bench. b.Now go to “Library Manager” and push create a new view:

7 The VLSI Systems Center - BGU The menu “Create New File” will appear: Choose “Tool” to be an “Hierarchy-Editor” and check that “View Name” changed to “config”, then click “ok”. The Hierarchy Editor will appear. c.In order to use Hierarchy Editor you need to set up few thinks: Set view to schematic (you can use, to do so, the browse button, fig-2). Set the “global bindings”:

8 The VLSI Systems Center - BGU Figure 2:

9 The VLSI Systems Center - BGU 1.“Library List”: Hear you should insert all libraries, that you make use of there ingredients (like:tsmc18sc – for standard cells you use in the design, or analogLib – for supply's that you use in the test). It is very important not to forget any of libraries, cause the Hierarchy Editor will not find the cell that in its library!!! (Figure 3)Figure 3 2.“View List”: First you should check which view’s it possible to use in your design and than insert all the possibilities to “View List” (for example: functional – you will use it in digital parts of the design). It is very important not to forget any of view’s, cause the Hierarchy Editor will not find the cell that use this view!!! (Figure 3)Figure 3 3.“Stop List”: Insert the views that you don’t want to see in Hierarchy Editor.

10 The VLSI Systems Center - BGU Figure 3 back

11 The VLSI Systems Center - BGU After doing all this your Hierarchy Editor configuration window will look like this: Now just click “ok”. That is the Hierarchy Editor you will finally get:

12 The VLSI Systems Center - BGU Now just save it and close every thing!

13 The VLSI Systems Center - BGU Hierarchy Editorwith Schematic. When it opened go to “Tools” in schematic and choose an “Analog environment”: III.Open the “config” view from Library Manager and choose to open Hierarchy Editor with Schematic. When it opened go to “Tools” in schematic and choose an “Analog environment”:

14 The VLSI Systems Center - BGU The icon of Analog Environment will appear: IV.Setting Analog Environment: 1.Choose the simulator you want to work with: In icon of Analog Environment go to “setup” -> “simulator/directory/host…”, the window “Choose simulator/directory/host…” will pop up:

15 The VLSI Systems Center - BGU Then click “ok” Choose “ams” simulator, your project directory, and host mode:

16 The VLSI Systems Center - BGU After you click “ok” you can notice that in schematic view now appears new field “AMS” and in the right upper corner of Analog Environment will be written “Simulator :“ams”

17 The VLSI Systems Center - BGU 2.Choosing the correct “Connect rules”: In Analog Environment go to “setup” -> “Connect rules”: The icon of “Select Connect Rules” will pop up:

18 The VLSI Systems Center - BGU If the rule that appears there not the correct one, you should delete it by choosing the rule and pushing delete button :

19 The VLSI Systems Center - BGU Then make sure you in “Built-in” mode and push “Customize…” button, the customization menu will pop up:

20 The VLSI Systems Center - BGU Choose there the relevant rule, check the parameters of it and click “ok”, it will bring you back to “connect rule” menu:

21 The VLSI Systems Center - BGU Click the “Add” button the rule you have chosed will appear in the window below. Now click “ok” to save your choice.

22 The VLSI Systems Center - BGU 3.Definition of the simulation models for your design: in “Analog Environment” choose “Setup” -> "Model Libraries”:

23 The VLSI Systems Center - BGU The “Model Libraries setup” will appear: Through “browse” button choose the Model Library you desire. Also you can enable and disable any library you need/don’t need in any time. The disabled one will appear with “#” at the left side. Click “ok” when it’s done.

24 The VLSI Systems Center - BGU 4.The Analyses definition: In Analog Environment choose “Analyses” -> “Choose…” The “Choosing Analyses” menu will pop up:

25 The VLSI Systems Center - BGU In this menu choose the needed Analysis (in our case it is ”tran”), and in the field of “Stop Time” insert the duration of the simulation. Enable your analysis and click “ok”.

26 The VLSI Systems Center - BGU In Analog Environment you can confirm that the analysis you’ve chosen is correct, it written in “Analyses” window:

27 The VLSI Systems Center - BGU 5.Variables Definition: In Analog Environment choose “Variables” -> “Copy From Cellview” : When it will finish copying, you will notice in the left bottom corner named “Design Variables” all the variables from your design (if you have any):

28 The VLSI Systems Center - BGU In our case it “Vin”. To define it’s voltage you can double click it, or in Analog Environment choose “Variables” -> “Edit” the Edit window will appear:

29 The VLSI Systems Center - BGU In the “Value (Expr)” field insert your value and click “change”, the value will appear in it’s field. Click “ok” when finished.

30 The VLSI Systems Center - BGU 6.Plot interest: if you need to plot and/or to save any net in your schematic, you need to choose : “Outputs” -> “To Be Plotted” -> “Select on Schematic”:

31 The VLSI Systems Center - BGU Now you can choose any net you want to be plotted at yours design, it’ll look like this: You can save the net thru “outputs”-> “setup” and choose the save button of every net you want to save

32 The VLSI Systems Center - BGU  Anyway you can decide to save all the nets in any hierarchy. To do so, in Analog Environment go to “Outputs”-> “Save All…”: The save menu will pop up:

33 The VLSI Systems Center - BGU Hear you can decide to save all nets in some levels (hierarchies), like the nets, and the currents. In this case we save: all nets in 3 upper levels and all currents in 2 upper levels. When you complete to configure it press “ok”.

34 The VLSI Systems Center - BGU 7.Solver definition: In Analog Environment choose “Simulation” -> “Solver”: The “Solver” window will pop up:

35 The VLSI Systems Center - BGU Choose your solver to be “UltraSim” and click “ok”.

36 The VLSI Systems Center - BGU 8.Run Options: First of all you can see that in the window of Analog Environment the simulator indication now says ams(UltraSim). Now you choose “Simulation”-> “Run Options…”: The pop up of “Run Options” window will appear now:

37 The VLSI Systems Center - BGU Select “All” against “Compile” & “Elaborate” “Incremental” to compile and elaborate all your design every time you doing netlist, check that you in the “Batch” mode and click “ok”. Also in “CIW” go to “tools”-> “AMS”-> “Options…”:

38 The VLSI Systems Center - BGU The Options menu will appear: In “Check and Save” category – mark :”AMS check, netlist and Compile AMS netlist. Click “Apply” when finished.

39 The VLSI Systems Center - BGU Now in the same menu go to “Compiler” and provide path to “hdl.var” you using. For edit “hdl.var” press the “Edit…” button, press “ok” when finished.

40 The VLSI Systems Center - BGU 9.The advantage of AMS that it provides you opportunity to run analog and digital parts in different precision. More precisely you can run every part of your design with different accuracy and speed. That's how you do it: a.First of all you decide, how precise will the simulator calculate, for all your design. To configure it go in “Analog Environment” to “Simulation”-> "Options”-> “FastSPICE(UltraSim)…”

41 The VLSI Systems Center - BGU The menu of “UltraSim options” will appear:

42 The VLSI Systems Center - BGU In “Simulation mode” field open the menu:

43 The VLSI Systems Center - BGU Hear you can decide the accuracy of calculation for all design together: Digital Fast (DF) – the fastest but least accurate. Spice (S) – most accurate but the slowest. The rest, like another 4 stages of accuracy and speed, that you can decide which one will be the best for your design. {In our design I have chosen “MS”, it is the accuracy I want for my analog part of the design.{

44 The VLSI Systems Center - BGU b.Second is to configure every part or cell separately, to do so, go to “Hierarchy Editor”-> “View” and choose “Properties”: This will open in H.E. additional properties. The property you need to see it’s “sim_mode”, it’s can be empty or like here contain some value.

45 The VLSI Systems Center - BGU Click the right button on the “sim_mode” against the needed cell (one of the top_level cells): Go to “Set “sim_mode” cell Property”. Now you can choose a needed “sim_mode”: The empty field is a “sim_mode” that we choose in “a” for all the design and the rest is the sim_modes we want to provide locally. (in our case we choose (df) for a digital part of the design).

46 The VLSI Systems Center - BGU After that we will see “df” against “controller” in blue and it’s necessary to do the update to Hierarchy Editor So press the update button that now appears with exclamation mark.

47 The VLSI Systems Center - BGU The update menu will pop up. Select your design and press “ok”. After it'll finish the Update, all sub cells of that specific cell (controller in our case) will become “df” also, but will be written in black, so you could separate which is the top hierarchy from all. You can see how it looks in the next slide.

48 The VLSI Systems Center - BGU Now the cell “controller” will run in “digital fast” mode. The same you can do with any cell you choose!

49 The VLSI Systems Center - BGU 10.Netlister: global signals to set the global signals first you should create a net list of your design. To do so go in Analog Environment to “simulation”-> “Options”-> “Netlist”->”Recreate”: If in CIW you’ll see that the process finished unsuccessful you should “check&save” the Schematic and update the Hierarchy Editor, than try to create the “Netlist” again (it’s very important to remember which part of your design was changed from last “check&save” so you could find it quicker).

50 The VLSI Systems Center - BGU After the Netlist created the CIW should look like this: Only now you can proceed and edit Global Signals of your design.

51 The VLSI Systems Center - BGU global signals. Now you can set the global signals. Go in Analog Environment to “Options”-> “Netlister…”: The “Netlister Options” window will pop up:

52 The VLSI Systems Center - BGU Push the “Global Signals…” button. The Global Signals menu will appear:

53 The VLSI Systems Center - BGU The signals that’s appears hear should be only global power or ground. If it’s a ground signal choose it and select ground button, then click “Change”.

54 The VLSI Systems Center - BGU Now all ground signals appears with “Yes” in “Ground” field. If you have global nets with same value, you can alias those nets, to do so click, holding “Ctrl”, on both signals with left button of the mouse, “Alias” menu will become available, so just click it. In the left side of aliased nets will appear “/-- & \--”. In the same way you can Unalias the nets. When you finish click “ok”.

55 The VLSI Systems Center - BGU 11.Save the state: It is recommended to save the state you prepared till here to prevent doing it every time you need to run this simulation! To do so, go in Analog Environment to “Session”-> “Save State…” The save menu will appear:

56 The VLSI Systems Center - BGU Insert the name for this state, also you can provide a description to remember better the differences between the states. Click “ok” when finished.

57 The VLSI Systems Center - BGU V.Run the Simulation: 1.To run the simulation go to “Simulation”-> “Netlist and Run”, or press on the green traffic light. If the netlist already was provided and no changes were made you can just run the simulation without Netlisting by clicking on “Run”, or yellow traffic light:

58 The VLSI Systems Center - BGU 2.Following the simulation run: you can follow the run by several ways: a.log window that pops up. b.CIW that gives you the completed stages. If every thing runs ok that's how should it look: 3. Known failures in compilation stage

59 The VLSI Systems Center - BGU 4. Known failures in elaboration stage

60 The VLSI Systems Center - BGU 5. Known failures in simulation stage

61 The VLSI Systems Center - BGU 6.

62 The VLSI Systems Center - BGU 7.When the simulation is complete the plot window will pop up, showing you the graphs that hade been plotted from the lines you have chosen. It looks something like this:

63 The VLSI Systems Center - BGU Compilation Failures 1.

64 The VLSI Systems Center - BGU Elaboration Failures a.Ncelab: *E, CUCFUN: instance’ ‘ of the unit ‘ ’ is unresolved in ‘ ’ 2. The solution to this failure: Probably one or several files disabled or don’t exist in your model library. You can enable or insert it like it described on page 22page 22

65 The VLSI Systems Center - BGU Simulation Failures a.Ncsim: *E, RNALER: simulation terminated due to analog error. 3. The solution to this failure: That failure is probably happens because exaggerated use of resources (CPU, Memory). The solution is to try to shutter the resource usage. My recommendation is to save less levels of outputs, that was described in page 32. Or try to lower the accuracy level like on pages 40 – 48. page

66 The VLSI Systems Center - BGU The End The End

67 The VLSI Systems Center - BGU II.Start building the Test a.Create “schematic view”Create “schematic view” b.Create “Config view”Create “Config view” c.Configuration of “Hierarchy Editor”Configuration of “Hierarchy Editor” Back to Topics

68 The VLSI Systems Center - BGU IV.Start building the Test 1.Choose the simulatorChoose the simulator 2.Choose “Connect rules”Choose “Connect rules” 3.Definition of the simulation modelsDefinition of the simulation models 4.The Analyses definitionThe Analyses definition 5.Variables DefinitionVariables Definition 6.Plot interestPlot interest 7.Solver definitionSolver definition 8.Run OptionsRun Options 9.Simulation accuracy definitionSimulation accuracy definition 10.NetlisterNetlister 11.Save the stateSave the state Back to Topics

69 The VLSI Systems Center - BGU 9.Simulation accuracy definition a.Accuracy Definition For All The DesignAccuracy Definition For All The Design b.Accuracy Definition For Every CellAccuracy Definition For Every Cell Back to Topics

70 The VLSI Systems Center - BGU VI.Failures & Solutions: 1.Compilation FailuresCompilation Failures a.D 2.Elaboration FailuresElaboration Failures a.D 3.Simulation FailuresSimulation Failures a.Ncsim: *E, RNALER: simulation terminated due to analog error.Ncsim: *E, RNALER: simulation terminated due to analog error. Back to Topics


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