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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 1 Vector Computers Muhamed Mudawar Computer Engineering Department King Fahd University of Petroleum and Minerals

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 2 + r1 r2 r3 add r3, r1, r2 SCALAR (1 operation) v1 v2 v3 + vector length addv v3, v1, v2 VECTOR (N operations) Vector processors have high-level operations that work on linear arrays of numbers: "vectors" Vector Processing

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 3 Vector Supercomputers Idealized by Cray-1, 1976: Scalar Unit + Vector Extensions Load/Store Architecture Vector Registers Vector Instructions Hardwired Control Highly Pipelined Functional Units Interleaved Memory System No Data Caches No Virtual Memory

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 4 Cray-1 (1976) memory bank cycle 50 ns processor cycle 12.5 ns (80MHz)

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 5 Single Port Memory 16 banks of 64-bit words + 8-bit SECDED 80MW/sec data load/store 320MW/sec instruction buffer refill 4 Instruction Buffers 64-bitx16 NIP LIP CIP (A 0 ) ( (A h ) + j k m ) 64 T Regs (A 0 ) ( (A h ) + j k m ) 64 B Regs S0 S1 S2 S3 S4 S5 S6 S7 A0 A1 A2 A3 A4 A5 A6 A7 SiSi T jk AiAi B jk FP Add FP Mul FP Recip Int Add Int Logic Int Shift Pop Cnt SjSj SiSi SkSk Addr Add Addr Mul AjAj AiAi AkAk V0 V1 V2 V3 V4 V5 V6 V7 VkVk VjVj ViVi V. Mask V. Length 64 Element Vector Registers Cray-1 (1976)

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 6 Vector Instruction Set Architecture ISA in general Operations, Data types, Format, Accessible Storage, Addressing Modes, Exceptional Conditions Vector ISA Operations Data types (Float, int, V op V, S op V) Format Source and Destination Operands Length Successor (consecutive, stride, indexed, gather/scatter) Conditional operations Exceptions

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 7 Styles of Vector Architectures Memory-memory vector processors: all vector operations are memory to memory CDC Star100, Cyber203, Cyber205, 370 vector extensions Vector-register processors: all vector operations between vector registers (except load and store) Vector equivalent of load-store architectures Introduced in the Cray-1 Includes all vector machines since late 1980s: Cray, Convex, Fujitsu, Hitachi, NEC We assume vector-register for the rest of lecture

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 8 Scalar Registers r0 r15 Vector Registers v0 v15 [0][1][2][VLRMAX-1] ++++++ [0][1][VLR-1] Vector Arithmetic Instructions ADDV v3, v1, v2 v3 v2 v1 VLR Vector Length Register v1 Vector Load and Store Instructions LV v1, r1, r2 Base, r1Stride, r2 Memory Vector Register Vector Programming Model

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 9 Instr.OperandsOperationComment ADDV V1,V2,V3V1=V2+V3vector + vector ADDSV V1,F0,V2V1=F0+V2scalar + vector MULTV V1,V2,V3V1=V2xV3vector x vector MULSV V1,F0,V2V1=F0xV2scalar x vector LV V1,R1V1=M[R1..R1+63]load, stride=1 LVWS V1,R1,R2V1=M[R1..R1+63*R2]load, stride=R2 LVI V1,R1,V2V1=M[R1+V2i,i=0..63] load, indexed CeqV VM,V1,V2VMASKi = (V1i=V2i)?comp. setmask MOV VLR,R1Vec. Len. Reg. = R1set vector length MOV VM,R1Vec. Mask = R1set vector mask Vector Instructions

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 10 Each result independent of previous result Long pipeline, compiler ensures no dependencies High clock rate Vector instructions access memory with known pattern Highly interleaved memory Amortize memory latency of over 64 elements No (data) caches required! (Do use instruction cache) Reduces branches and branch problems in pipelines Single vector instruction implies lots of work ( loop) Fewer instruction fetches Properties of Vector Processors

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 11 # Scalar Code LI R4, 64 loop: L.D F0, 0(R1) L.D F2, 0(R2) ADD.D F4, F2, F0 S.D F4, 0(R3) ADDIU R1, 8 ADDIU R2, 8 ADDIU R3, 8 SUBIU R4, 1 BNEZ R4, loop # Vector Code LI VLR, 64 LV V1, R1 LV V2, R2 ADDV V3, V1, V2 SV V3, R3 # C code for (i=0; i<64; i++) C[i] = A[i] + B[i]; Vector Code Example

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 12 Compact one short instruction encodes N operations Expressive, tells hardware that these N operations: Are independent Use the same functional unit Access disjoint registers Access registers in the same pattern as previous instructions Access a contiguous block of memory (unit-stride load/store) Access memory in a known pattern (strided load/store) Scalable Can run same object code on more parallel pipelines or lanes Vector Instruction Set Advantages

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 13 Components of a Vector Processor Vector Register File Has at least 2 read and 1 write ports Typically 8-32 vector registers Each holding 64 (or more) 64-bit elements Vector Functional Units (FUs) Fully pipelined, start new operation every clock Typically 4 to 8 FUs: FP add, FP mult, FP reciprocal Integer add, logical, shift (multiple of same unit) Vector Load-Store Units (LSUs) Fully pipelined unit to load or store a vector May have multiple LSUs Scalar registers Single element for FP scalar or address Cross-bar to connect FUs, LSUs, registers

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 14 Machine Year Clock Regs Elements FUs LSUs Cray 1197680 MHz86461 Cray XMP1983120 MHz86482L, 1S Cray YMP1988166 MHz8648 2L, 1S Cray C-901991240 MHz812884 Cray T-901996455 MHz812884 Conv. C-1198410 MHz812841 Conv. C-41994133 MHz1612831 Fuj. VP2001982133 MHz8-25632-102432 Fuj. VP3001996100 MHz8-25632-102432 NEC SX/21984160 MHz8+8K256+var168 NEC SX/31995400 MHz8+8K256+var168 Examples of Vector Machines

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 15 Vector Arithmetic Execution Use deep pipeline (=> fast clock) to execute element operations Simplifies control of deep pipeline because elements in vector are independent No hazards! V1V1 V2V2 V3V3 V3 <- v1 * v2 Six stage multiply pipeline

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 16 Vector Memory System Cray-1: 16 banks 4 cycle bank busy time Bank busy time: Cycles between accesses to same bank 12 cycle latency + BaseStride 0123456789ABCDEF Vector Registers Memory Banks Address Generator

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 17 Great for unit stride: Contiguous elements in different DRAMs Startup time for vector operation is latency of single read What about non-unit stride? Above good for strides that are relatively prime to 8 Bad for strides = 2, 4 and worse for strides = multiple of 8 Better: prime number of banks…! Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Unpipelined DRAM Addr+0 Addr+1 Addr+2Addr+4Addr+5Addr+3 Addr+6 Addr+7 Interleaved Memory Layout

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 18 ADDV C,A,B C[1] C[2] C[0] A[3]B[3] A[4]B[4] A[5]B[5] A[6]B[6] Execution using one pipelined functional unit C[4] C[8] C[0] A[12]B[12] A[16]B[16] A[20]B[20] A[24]B[24] C[5] C[9] C[1] A[13]B[13] A[17]B[17] A[21]B[21] A[25]B[25] C[6] C[10] C[2] A[14]B[14] A[18]B[18] A[22]B[22] A[26]B[26] C[7] C[11] C[3] A[15]B[15] A[19]B[19] A[23]B[23] A[27]B[27] Execution using four pipelined functional units Vector Instruction Execution

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 19 Vector Unit Structure Lane Functional Unit Vector Registers Memory Subsystem Elements 0, 4, 8, … Elements 1, 5, 9, … Elements 2, 6, 10, … Elements 3, 7, 11, …

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 20 33 Vector register file Each register is an array of elements Size of each register determines maximum vector length Vector length register determines vector length for a particular operation Multiple parallel execution units = “lanes” Sometimes called “pipelines” or “pipes” Vector Unit Implementation

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 21 LaneVector register elements striped over lanes [0] [8] [16] [24] [1] [9] [17] [25] [2] [10] [18] [26] [3] [11] [19] [27] [4] [12] [20] [28] [5] [13] [21] [29] [6] [14] [22] [30] [7] [15] [23] [31] T0 Vector Microprocessor (1995) See http://www.icsi.berkeley.edu/real/spert/t0- intro.html http://www.icsi.berkeley.edu/real/spert/t0- intro.html

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 22 for (i=0; i < N; i++) C[i] = A[i] + B[i]; load add store load add store Iter. 1 Iter. 2 Scalar Sequential Code Vectorization is a massive compile-time reordering of operation sequencing requires extensive loop dependence analysis Vector Instruction load add store load add store Iter. 1 Iter. 2 Vectorized Code Time Automatic Code Vectorization

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 23 Problem: Vector registers have fixed length What to do if Vector Length > Max Vector Length? Stripmining: generate code such that each vector operation is done for a size ≤ MVL First loop iteration: do short piece (n mod MVL) Remaining iterations: VL = MVL index = 0; /* start at index 0 */ VL = (n mod MVL) /* find the odd size piece */ while (n > 0) { /* do vector instructions on VL elements */ n = n – VL; index = index + VL; VL = MVL /* reset the length to max */ } Vector Stripmining

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 24 ANDI R1, N, 63 # N mod 64 MOV VLR, R1 # Do remainder loop: LV V1, RA SLL R2, R1, 3 # Multiply by 8 ADDU RA, RA, R2 # Advance pointer LV V2, RB ADDU RB, RB, R2 ADDV V3, V1, V2 SV V3, RC ADDU RC, RC, R2 SUBU N, N, R1 # Subtract elements LI R1, 64 MOV VLR, R1 # Reset full length BGTZ N, loop # Any more to do? for (i=0; i

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 25 Two components of vector startup penalty Functional unit latency: time through pipeline Dead time: time before another vector instruction can use same pipelined functional unit RXXXW RXXXW RXXXWRXXXX RXXXX RXXXXRXXXXRXXXW RXXXW RXXXW Functional Unit Latency = 1 Read cycle, 3 eXecute cycles, and 1 Write cycle Dead Time First Vector Instruction 2nd Vector Instruction Vector Startup Dead Time

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 26 Dead Time and Short Vectors Cray C90, Two lanes 4-cycle dead time Maximum efficiency 94% with 128 element vectors T0, Eight lanes No dead time 100% efficiency with 8 element vectors No dead time 4-cycle dead time 64 cycles active Dead time reduces the maximum efficiency Can be eliminated with better control logic and fully pipelining instruction startup

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 27 Vector version of register bypassing Introduced with Cray-1 Memory V1V1 Load Unit Mult. V2V2 V3V3 Chain Add V4V4 V5V5 Chain LV v1 MULV v3,v1,v2 ADDV v5,v3,v4 Vector Chaining

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 28 Vector Chaining Advantage With chaining, can start dependent instruction as soon as first result appears Load Mul Add Load Mul Add Time Without chaining, must wait for last element of result to be written before starting dependent instruction

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 29 Vector Instruction Parallelism Can overlap execution of multiple vector instructions Example: 32 elements per vector register and 8 lanes load Load Unit mul Multiply Unit add Add Unit load time Instruction issue Complete 24 operations/cycle while issuing 1 short instruction/cycle muladd

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 30 Vector Execution Time depends on: Vector length, data dependences, and structural hazards Initiation rate Rate at which a vector unit consumes vector elements Typically, initiation rate = number of lanes Execution time of a vector instruction = VL / Initiation Rate Convoy Set of vector instructions that can execute in same clock No structural or data hazards (similar to VLIW concept) Chime Execution time of one convoy m convoys take m chimes = approximately m x n cycles If each chime takes n cycles and no overlapping convoys Vector Execution Time

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 31 LVV1, Rx; Load vector X MULVSV2, V1, F0; vector-Scalar multiply LVV3, Ry; Load vector Y ADDVV4, V2, V3; Add vectors SVRy, V4; Store result in vector Y 4 Convoys => 4 Chimes 1.LV 2.MULVS, LV 3.ADDV 4.SV Suppose VL=64 For 1 Lane:Chime = 64 cycles For 2 Lanes:Chime = 32 cycles For 4 Lanes:Chime = 16 cycles Example on Convoys and Chimes

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 32 Vector startup comes from pipeline latency Important source of overhead, so far ignored Startup time = depth of pipeline Increases the effective time to execute a convoy Time to complete a convoy depends Vector startup, vector length, number of lanes OperationStart-up penalty (from CRAY-1) Vector load/store12 cycles Vector multiply7 cycles Vector add6 cycles Startup penalty for load/store can be very high (100 cycles) Vector Startup

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 33 Consider same example with 4 convoys Vector length = n Assume Convoys don’t overlays Show the time of each convoy assuming 1 lane ConvoyStart timeFirst resultLast result 1. LV 01211 + n 2. MULVS, LV12 + n12 + n + 1223 + 2n 3. ADDV24 + 2n24 + 2n + 629 + 3n 4. SV 30 + 3n30 + 3n + 1241 + 4n Example on Vector Startup Total cycles = 42 + 4n (with extra 42 startup cycles)

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 34 Suppose: MULVV1, V2, V3 ADDVV4, V1, V5; RAW dependence Chaining: Allow a vector operation to start as soon as the individual elements of the vector source operands become available. Forward individual elements of a vector register. Dependent instructions can be placed in the same convoy (if no structural hazard) MULTV ADDV Total = 141 cycles 128/141 = 0.91 Flops/cycle 764 6 Unchained = 2 convoys Total = 77 cycles 1.66 Flops/cycle MULTV ADDV 764 6 Chained = 1 convoy Vector Chaining

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 35 Vector Stride Adjacent elements are not sequential in memory do 10 i = 1,100 do 10 j = 1,100 A(i,j) = 0.0 do 10 k = 1,100 10A(i,j) = A(i,j) + B(i,k) * C(k,j) Either B or C accesses are not adjacent 800 bytes between adjacent vector elements Stride: distance separating elements that are to be merged into a single vector Caches do unit stride LVWS (load vector with stride) instruction Think of addresses per vector element

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 36 Memory Addressing Modes Load/store operations move groups of data between registers and memory Three types of vector addressing Unit stride Contiguous block of information in memory Fastest: always possible to optimize this Non-unit (constant) stride Harder to optimize memory system for all possible strides Prime number of data banks makes it easier to support different strides at full bandwidth Indexed (gather-scatter) Vector equivalent of register indirect Good for sparse arrays of data Increases number of programs that vectorize

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 37 Vector Scatter/Gather Want to vectorize loops with indirect accesses for (i=0; i

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 38 Vector Scatter/Gather Scatter example: for (i=0; i

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 39 Memory Banks Most vector processors support large number of independent memory banks Memory banks are need for the following reasons Multiple Loads/Stores per cycle Memory bank cycle time > CPU cycle time Ability to load/store non-sequential elements Multiple processor sharing the same memory Each processor generates its stream of load/store instructions

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 40 Example on Memory Banks The Cray T90 has a CPU cycle = 2.167 ns The cycle of the SRAM in memory system = 15 ns Cray T90 can support 32 processors Each processor is capable of generating 4 loads and 2 stores per CPU clock cycle What is the number of memory banks required to allow all CPUs to run at full memory bandwidth Solution: Maximum number of memory references per cycle 32 CPUs x 6 references per cycle = 192 Each SRAM busy is busy for 15 / 2.167 = 6.92 ≈ 7 cycles To handle 192 requests per cycle requires 192 x 7 = 1344 memory banks Cray T932 actually has 1024 memory banks

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 41 Problem: Want to vectorize loops with conditional code: for (i=0; i

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 42 Vector Masks Vector masks have two important uses Conditional execution and arithmetic exceptions Alternative is conditional move/merge More efficient than conditional moves No need to perform extra instructions Avoid exceptions Downside is: Extra bits in instruction to specify the mask register For multiple mask registers Extra interlock early in the pipeline for RAW hazards

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 43 Masked Vector Instructions C[4] C[5] C[1] Write data port A[7]B[7] M[3]=0 M[4]=1 M[5]=1 M[6]=0 M[2]=0 M[1]=1 M[0]=0 M[7]=1 Density-Time Implementation Scan mask vector and Execute only elements with Non-zero masks C[1] C[2] C[0] A[3]B[3] A[4]B[4] A[5]B[5] A[6]B[6] M[3]=0 M[4]=1 M[5]=1 M[6]=0 M[2]=0 M[1]=1 M[0]=0 Write data portWrite Enable A[7]B[7]M[7]=1 Simple Implementation Execute all N operations Turn off result writeback according to mask

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 44 Compress: Packs non-masked elements from one vector register contiguously at start of destination vector register Population count of mask vector gives packed vector length Used for density-time conditionals and for general selection Expand: performs inverse operation M[3]=0 M[4]=1 M[5]=1 M[6]=0 M[2]=0 M[1]=1 M[0]=0 M[7]=1 A[3] A[4] A[5] A[6] A[7] A[0] A[1] A[2] M[3]=0 M[4]=1 M[5]=1 M[6]=0 M[2]=0 M[1]=1 M[0]=0 M[7]=1 B[3] A[4] A[5] B[6] A[7] B[0] A[1] B[2] Expand A[7] A[1] A[4] A[5] Compress A[7] A[1] A[4] A[5] Compress/Expand Operations

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 45 Problem: Loop-carried dependence on reduction variables sum = 0; for (i=0; i

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 46 Multimedia Processing: compress, graphics, audio, images Standard benchmark kernels: Matrix Multiply, FFT, Sort Lossy Compression: JPEG, MPEG video and audio Lossless Compression: Zero removal, RLE, Differencing, LZW Cryptography: RSA, DES/IDEA, SHA/MD5 Speech and handwriting recognition Operating systems/Networking: memcpy, parity, checksum Databases: hash/join, data mining, image/video serving Language run-time support: stdlib, garbage collection Vector Applications

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 47 “…media processing will become the dominant force in computer architecture & microprocessor design.” “... new media-rich applications... involve significant real-time processing of continuous media streams, and make heavy use of vectors of packed 8-, 16-, and 32-bit integer and FP” Needs include high memory BW, high network BW, continuous media data types, real-time response, fine grain parallelism “How Multimedia Workloads Will Change Processor Design”, Diefendorff & Dubey, IEEE Computer (9/97) New Architecture Direction?

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 48 Multimedia Extensions Very short vectors added to existing ISAs for micros Intel MMX: reuses 64-bit FP registers Split into 2x32b, 4x16b or 8x8b Add, Subtract in parallel: 8x8b, 4x16b, 2x32b Optional signed/unsigned saturate if overflow Shifts (sll,srl, sra) in parallel: 8x8b, 4x16b, 2x32b Multiply, Multiply-Add in parallel: 4x16b Compare =, > in parallel: 8x8b, 4x16b, 2x32b Sets field to 0s (false) or 1s (true); removes branches Pack/Unpack Convert 32b ↔ 16b, 16b ↔ 8b Pack saturates (set to max) if number is too large

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 49 Multimedia Extensions – cont’d Newer designs have 128-bit registers (Altivec, SSE2) Limited instruction set: No vector length control No strided load/store or scatter/gather Unit-stride loads must be aligned to 64/128-bit boundary Limited vector register length: Superscalar dispatch to keep multiply/add/load units busy Loop unrolling to hide latencies increases register pressure Trend towards full vector support in microprocessors

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 50 Emotion Engine: 6.2 GFLOPS, 75 million polygons per second Graphics Synthesizer: 2.4 Billion pixels per second Claim: Toy Story realism brought to games! Sony Playstation 2000

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 51 Sample Vector Unit 2-wide VLIW Includes Microcode Memory High-level instructions like matrix-multiply Emotion Engine: Superscalar MIPS core Vector Coprocessor Pipelines RAMBUS DRAM interface Playstation 2000 – Continued

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 52 CMOS Technology 500 MHz CPU, fits on single chip SDRAM main memory (up to 64GB) Scalar unit 4-way superscalar, out-of-order and speculative 64KB I-cache and 64KB data cache Vector unit 8 foreground VRegs + 64 background VRegs 256x64-bit elements/VReg 1 multiply, 1 divide, 1 add/shift, 1 logical, 1 mask unit 8 lanes (8 GFLOPS peak, 16 FLOPS/cycle) 1 load & store unit, 32x8 byte accesses/cycle, 32 GB/s bandwidth SMP structure 8 CPUs connected to memory through crossbar 256 GB/s shared memory bandwidth (4096 interleaved banks) A Modern Vector Super Computer: NEC SX-6 (2003)

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 53 Vector One instruction fetch, decode, dispatch per vector Structured register accesses Smaller code for high performance, less power in instruction cache misses Bypass data cache One TLB lookup per group of loads or stores Move only necessary data across chip boundary Single-issue Scalar One instruction fetch, decode, dispatch per operation Arbitrary register accesses adds area and power Loop unrolling and software pipelining for high performance increases instruction cache footprint All data passes through cache, waste power if no temporal locality One TLB lookup per load or store Off-chip access in whole cache lines Scalar versus Vector Energy Efficiency

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 54 Vector Control logic grows linearly with issue width N ops issued per cycle 2 ) circuitry Vector unit switches off when not in use Vector instructions expose parallelism without speculation Software control of vector masks or compress/expand for conditionals Superscalar Control logic grows quadratically with issue: N ops issued per cycle 2 ) circuitry Control logic consumes energy regardless of available parallelism Speculation wastes energy to increase visible parallelism Superscalar Energy Efficiency

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CSE 661 - Parallel and Vector ArchitecturesVector Computers – slide 55 Summary Vector is a model for exploiting Data Parallelism If code is vectorizable, then simpler hardware, more energy efficient, and better real-time model than Out-of-order machines Design issues include number of lanes, number of functional units, number of vector registers, length of vector registers, exception handling, and conditional operations Fundamental design issue is memory bandwidth With virtual address translation and caching Will multimedia popularity revive vector architectures?

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CPE 631: Vector Processing (Appendix F in COA4)

CPE 631: Vector Processing (Appendix F in COA4)

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