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© 2004, D. J. Foreman 1 Basic Synchronization Semaphores
© 2004, D. J. Foreman 2 One Problem (of many) T1T2 count++ //compiles as:count-- //compiles as: register1 = countregister2 = count register1 = register1 + 1 register2 = register2 - 1 count = register1count = register2 What if an interrupt occurs and t2 gets control? This is a “Critical Section” Incorrect values of "count" can result due to time-slicing How do we prevent such errors Note: "count" is global
© 2004, D. J. Foreman 3 Conditions/Requirements n processes competing for shared data Each process has a code segment, called a critical section, (CS) which uses the shared data Must guarantee: ■ only 1 thread may be in its critical section at a time ■ Only a thread inside a CS may determine if a thread may enter ■ Bounded waiting (no starvation)
© 2004, D. J. Foreman 4 Solution Proposals 1. Turn interrupts off (not MP safe) 2. Flag in kernel to disallow context switch (works for kernel routines too) (MP safe) 3. Semaphores (MP safe) ■ Implemented as h/w inst ■ 80x86 has XCHG (not MP safe) Swaps RAM & register in 1 inst cycle not 1 bus cycle 4. Busy wait or “spin lock”..\..\552pages\slides\addenda\Classical Solutions to Mutual Exclusion.pptx
© 2004, D. J. Foreman 5 Clever S/W-Only Solution Shared memory int flag [0..1]; int turn Process 0 code flag := T; turn := 1; while (flag  and turn =1) do no-op; critical section flag := F;
© 2004, D. J. Foreman 6 Semaphores Sometimes called an “indivisible test and set.” In 80x86 - XCHG, swaps 1 RAM location and a register in one instruction cycle (but not one bus cycle – so not useful in multi-processor environments – unless enhanced.) Flag – global – initially 0 WAITMOVAX,1 XCHGFLAG,AX CMPAX,1 JEWAIT ---- critical section MOVFLAG,0
© 2004, D. J. Foreman 7 Spin Locks While (flag); // loops until flag=0 Wastes CPU time Makes user seem “bad”
© 2004, D. J. Foreman 8 Another Critical Section Problem Loadr1,bal Loadr2,amount Addr1,r2 Storer1,bal Loadr1,bal Loadr2,amount Subr1,r2 Storer1,bal p1, p2 are in a race bal=bal + amount bal=bal - amount interrupt context-switch
© 2004, D. J. Foreman 9 Locking a Critical Section While(lock) wait; lock=true Loadr1,bal Loadr2,amount Addr1,r2 Storer1,bal lock=false While(lock) wait; lock=true; Loadr1,bal Loadr2,amount Subr1,r2 Storer1,bal lock=false bal=bal + amountbal=bal - amount
© 2004, D. J. Foreman 10 Wait & Signal Classical definitions ■ Wait – Originally was P(s) DO WHILE (s<=0) // make me wait wait;// The wait is interruptible s=s-1; ■ Signal - Originally was V(s) s=s+1; // tell others I'm done Remember: these must appear as ATOMIC operations to the application "s" is global
© 2004, D. J. Foreman 11 Strategies 1. User-only mode software 2. Disabling interrupts 3. H/W & O/S support
© 2004, D. J. Foreman 12 Acceptable Solutions 1. One process at a time in CritSec 2. Entry decision made by entrants 3. No indefinite wait allowed 4. Limit to predecessors
© 2004, D. J. Foreman 13 Additional Problems Semaphores only protect the CritSec Signaling adds need for more semaphores Classical problems: ■ Bounded Buffer also known as Producer-Consumer ■ Readers & Writers Readers have precedence Writers have precedence
© 2004, D. J. Foreman 1 Basic Synchronization Semaphores.
© 2004, D. J. Foreman 1 Basic Synchronization. © 2004, D. J. Foreman 2 The Problem Given: "i" is global i++; expands into: LDAi ADAi,1 STAi What.
Chapter 6: Process Synchronization. 6.2 Silberschatz, Galvin and Gagne ©2005 Operating System Concepts – 7 th Edition, Feb 8, 2005 Objectives Understand.
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6.3 Peterson’s Solution The two processes share two variables: Int turn; Boolean flag The variable turn indicates whose turn it is to enter the critical.
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5.6 Semaphores Semaphores –Software construct that can be used to enforce mutual exclusion –Contains a protected variable Can be accessed only via wait.
Adopted from and based on Textbook: Operating System Concepts – 8th Edition, by Silberschatz, Galvin and Gagne Updated and Modified by Dr. Abdullah Basuhail,
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Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition Chapter 6: Process Synchronization.
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