Presentation is loading. Please wait.

Presentation is loading. Please wait.

S&IP Consortium Course Material On-Chip Bus Speaker: Tian-Sheuan Chang July, 2004.

Similar presentations


Presentation on theme: "S&IP Consortium Course Material On-Chip Bus Speaker: Tian-Sheuan Chang July, 2004."— Presentation transcript:

1 S&IP Consortium Course Material On-Chip Bus Speaker: Tian-Sheuan Chang July, 2004

2 2 S&IP Consortium Course Material Goal of This Lab  Understand how AHB-Lite works.  Learn how to add new slaves.  Learn to verify AHB-Lite compliance of a slave.

3 3 S&IP Consortium Course MaterialOutline  AMBA AHB system  AHB-Lite system  AHB compliance verification  Lab – On-chip bus: AHB-Lite

4 4 S&IP Consortium Course Material Typical AMBA system

5 5 S&IP Consortium Course Material An AHB System HSEL_x HGRANT_x HBUSREQ_x

6 6 S&IP Consortium Course Material Components in AHB (1/2)  Master  AHB master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16)  Slave  AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer.

7 7 S&IP Consortium Course Material Components in AHB (2/2)  Arbiter  AHB arbiter ensures that only one bus master at a time is allowed to initiate data transfers.  Decoder  AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.

8 8 S&IP Consortium Course Material AHB Signals  AHB Signals can be classified as  Clock (HCLK)  Address and read/write data (HADDR, HRDATA, HWDATA)  Arbitration (HGRANTx, HMASTER, HMASTLOCK,…)  Control signal (HRESETn,…)  Response signal(HREADY, HRESP)

9 9 S&IP Consortium Course Material AHB Transfer Signals  Transfer signals  HCLK  bus clock. All signal timings are related to the rising edge.  HADDR[31:0]  32 bits system bus  HWDATA/HRDATA [31:0]  32 bits write/read data bus  HWRITE  High: write data  Low: read data  HREADY  Transfer done

10 10 S&IP Consortium Course Material AHB Basic Transfer  Each transfer consists of  An address and control cycle  One or more cycles for the data

11 11 S&IP Consortium Course Material AHB Control Signals  Control signals  HTRANS[1:0]  Current transfer type  HBURST[2:0]  When sequential transfer, control transfer relation  HSIZE[2:0]  Control transfer size=2^HSIZE bytes(max=1024bits)  HPROT[3:0]  Protection data

12 12 S&IP Consortium Course Material AHB Control Signal - HTRANS  HTRANS[1:0]  IDLE: master don’t need data to be transfered  BUSY: allows bus masters to insert IDLE cycles in the middle of bursts of transfers.  NONSEQ: The address and control signals are unrelated to the previous transfer.  SEQ: the address is related to the previous transfer.

13 13 S&IP Consortium Course Material AHB Signals - HBURST

14 14 S&IP Consortium Course Material AHB Signals - HBURST

15 15 S&IP Consortium Course Material AHB Response Signals  Response signals  HREADY  Transfer done, ready for next transfer  HRESP[1:0]  OKAY transfer complete  ERROR transfer failure(ex: write ROM)  RETRY higher priority master can access bus  SPLIT other master can access bus

16 16 S&IP Consortium Course Material AHB Arbitration Signals  Arbitration signals  HGRANTx  Select active bus master  HMASTER[3:0]  Multiplex signals that sent from master to slave  HMASTLOCK  Locked sequence

17 17 S&IP Consortium Course Material Master Signals

18 18 S&IP Consortium Course Material Arbiters Signals

19 19 S&IP Consortium Course Material Slave Signals

20 20 S&IP Consortium Course MaterialOutline  AMBA AHB system  AHB-Lite system  AHB compliance verification  Lab5 – On-chip bus: AHB-Lite

21 21 S&IP Consortium Course Material Logic Module Memory Map

22 22 S&IP Consortium Course Material LM AHB-Lite Block Diagram

23 23 S&IP Consortium Course Material Integrator LM Block Diagram

24 24 S&IP Consortium Course Material Notes about LM AHB-Lite system  LM AHB-Lite is a slave in Integrator system  Uses bi-directional tri-state signals  HDATA  SDATA  HREADY  AHB ZBT SRAM controller needs ZBT to be able to read/write without dead cycle.  HREADY always HIGH  No wait-state access  ZBT  Zero Bus Turn-around

25 25 S&IP Consortium Course Material Modified AHB-Lite system(1/1)  Modified from LM AHB-Lite system  Replaced bi-directional signal with independent input and output signals  HDATA  HWDATA/HRDATA  SDATA  SWDATA/SRDATA  HREADY  HREADYout/HREADY (internal)

26 26 S&IP Consortium Course Material Modified AHB-Lite system(2/2)  Added 2 more modules  AHB_HC_master  Master module to drive test pattern to AHB-Lite  SRAM_8X8X4096  Connected to ZBT SRAM controller  Limitation: 16 KB (originally was 1MB on LM) Cannot perform read after write immediately due to AHB pipeline access characteristic.  Removed some signals (pins)  Flash related signals  TDI, TDO, RTCK, etc.

27 27 S&IP Consortium Course Material AHB-Lite system diagram

28 28 S&IP Consortium Course Material AHB-lite Access (2/2)  Master checks HREADYin  HREADYin LO: hold control  HREADYin HI: initiates access request  Read/write  Transfer type  Transfer size  Decoder decodes access address  HDRID=0xC  First LM  HADDR[27:20]= 0x20  ZBT SRAM controller  HSEL_zbtssram=1’b1  send slave select signal

29 29 S&IP Consortium Course Material AHB-lite Access (1/2)  ZBT SRAM controller  Write: master send HWDATA to slave in data phase  Read: slave returns HRDATA to MUX  MUX slave to master read data:  HSEL_zbtssram=1’b1  select HRDATA from ZBT SRAM controller to send to master  Ready signals  Response signals

30 30 S&IP Consortium Course MaterialOutline  AMBA AHB system  AHB-Lite system  AHB compliance verification  Lab – On-chip bus: AHB-Lite

31 31 S&IP Consortium Course Material Compliance check method (1/2)  Simulation check (coverage driven)  Create check list according to specification  Create test pattern to hit all the cases in check list  Synopsys DesignWare Verification IP (VIP) + Vera  ARM AMBA Compliance Test-bench (ACT)  Manually check (most error prone)  May not cover some corner case  100% coverage (of check list) does not suggest 100% proven

32 32 S&IP Consortium Course Material Compliance check method (2/2)  Formal techniques  Property and rules extraction  Model & property checking and state space exploration  Averants Solidify SolidAHB  If rules are 100% proven, the interface will not violate the rules

33 33 S&IP Consortium Course Material Example of check list from DesignWare VIP  State cases State Name # defined values # hits cv_nseq_rd126 cv_seq_rd114 cv_busy_rd13 cv_nseq_wr19 cv_seq_wr18 cv_busy_wr12  Transition cases Transition Name # defined transitions # hits cv_nseq2nseq 1 22 cv_nseq2seq 1 5 cv_nseq2idle 1 3 cv_nseq2busy 1 3 cv_seq2seq 113

34 34 S&IP Consortium Course MaterialOutline  AMBA AHB system  AHB-Lite system  AHB compliance verification  Lab -On-chip bus: AHB-Lite

35 35 S&IP Consortium Course Material Lab : On-chip bus: AHB-Lite  Goal  Familiarize AHB using AHB-Lite  Learn how to add new slave into AHB-Lite  Practice checking the compliance of an AHB-Lite slave  Principles  AMBA Protocols  Guidance  Observer the AHB read/write  Identify which module defines the memory map  Steps  Run the example AHB-Lite  Observe signals  Requirements and Exercises  Add a new slave  Check AHB-Lite compliance of the new slave  Discussion  Disadvantage of using AMBA AHB (Overhead)

36 36 S&IP Consortium Course Material Files Descriptions  Modify AHB_HC_master.v to modify test pattern  Modify AHB_Testbench.v to modify simulation cycles  Modify AHB_Testbench.f to add new files  MyIP.v is the new slave to be added into AHB-Lite FilesPathDescription AMBA_declare.v /behAMBA related predefined keywords AHB_HC_master.v /behAHB_HC_master behavioral module SRAM_8X4X4096.v /beh16KB SRAM module RA1SH.v /behSRAM behavioral model AHB_Testbench.v /beh AHB_Testbench top module including AHB_HC_master, SRAM_8X4X4096, and RA1SH AHBAHBTop.v /rtlAHBAHBTop modified module AHBDecoder.v /rtlAHBDecoder module AHBMuxS2M.v /rtlAHBMuxS2M module AHBZBTRAM.v /rtlAHBZBTRAM module AHB2APB.v /rtlAHB2APB module, it is also a slave AHBAPBSys.v /rtlAHBAPBSys module APBRegs.v /rtlAPBRegs module APBIntcon.v /rtlAPBIntcon module MyIP.v /rtlSlave to be added into AHB-Lite AHB_Testbench.f /verifFile lists of the whole test bench LM_AHBAPB.f /verifFile lists of AHBAHBTop and its sub- modules

37 37 S&IP Consortium Course Material Accesses made by AHB_HC_master  7 Accesses  Data and control are not within the same cycle No.HWRITEHSIZEHADDRHRDATA/ HWDATA Remarks 1Read32-bit 0xc xXXXXXXXX 2Read32-bit 0xc xXXXXXXXX 3Write32-bit 0xc x Read32-bit 0xc x SRAM cannot read immediately after write using ZBT SRAM controller. 5Read32-bit 0xc xXXXXXXXX 6Read32-bit 0xc x Read32-bit 0xc xXXXXXXXX

38 38 S&IP Consortium Course Material Lab Requirements for Students  Run the modified AHB-Lite system using verilog simulator  Use Debussy nWave to observe the AHB signals during the 7 accesses intiated by AHB_HC_master.  Explain the waveforms to TA, they must point out the pipeline transfer characteristic of AHB bus.

39 39 S&IP Consortium Course Material Lab Exercise for Students  Add a new slave device: MyIP to the modified AHB- Lite system.  MyIP is a slave device provided for exercise  Verify the slave’s AHB compliance  Make check lists  Nonseq_16_write, write_after_read_16, etc.  Write test pattern to check the check list for compliance

40 40 S&IP Consortium Course MaterialReferences [1] AMBA Specification, Rev. May, 2.0, [2] High-Speed Single-Port SRAM (HS-SRAM-SP) Generator User Manual, Artisan Components Inc., Release 4.0, Aug [3] Debussy User Guide and Tutorial, NOVAS Software Inc., Sept [4] Compatibility of Network SRAM and ZBT SRAM, Mitsubishi LSIs Application Note (AP-S001E), Rev. C, Renesas Tech. Corp., Sept [5] DesignWare AHB Verification IP Databook, ver. 2.0a, Synopsys Inc., July [6] VMT User Manual, Release 2.0a, Synopsys Inc., July [7] Vera User Guide, ver. 5.1, Synopsys Inc., June [8] SolidAMBA, Averant Inc., Dec


Download ppt "S&IP Consortium Course Material On-Chip Bus Speaker: Tian-Sheuan Chang July, 2004."

Similar presentations


Ads by Google