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Functionally Linear Decomposition and Synthesis (FLDS) of Logic Circuits for FPGAs @Tomasz S. Czajkowski and Stephen D. Brown,IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008 Vishesh Kalra EE800 11089943 Vishesh Kalra EE800 11089943

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Earlier Method’s Transforms >Logic function->Different Domains->Analysis Binary Decision Diagrams(BDD) Linear(OR/XOR) and Non Linear(AND/OR/NOT) More Recently Davio and Shanon’s for XOR based Decomposition

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Introduction XOR based Logic Synthesis Approach. Methods >Gaussian Elimination >Binary Decision Diagrams to represent Logic functions

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Concept of Linearity >F(x)=∑G i (y)*H i (x-y) >X,Y are set of Variables(Y≤X). > ∑ represents XOR gate. >F is weighted sum of functions of G i (Basis), where weighting factors are determined by H i (Selector). This retains ability to synthesize original function using Davio/Shanon’s as well as BDD.

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Concept of Vector Space 1 0 2 6 2 0 1 3 5 2 0 0 0 0 0 Two Left most vectors are known as “Basis”

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Concept of Vector Space Suppose we have a vector 1 -3 4 -2 5 4 Gaussian Elimination 2 -6 9 -1 8 2 -------------------------- 2 -6 9 -1 9 7 -1 3 -4 2 -5 -4 1 -3 4 -2 5 4 0 0 1 3 -2 -6 0 0 0 0 1 5 0 0 0 0 0 0

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Basis 1 4 5 2 9 8 2 9 9 -1 -4 -5

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Truth Table Decomposition Gaussian Elimination BASIS VECTOR

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Synthesis G 1 =c; G 2 =d; Next Step-Try Express entire truth table as combination of these two vectors(Basis Vectors) Expressing each Column as h 1i G 1 (XOR)h 2i G 2 To find h 1i and h 2i we solve linear equation of the form Ax=B; A=[G 1 G 2 ],x=[h 1i h 2i ] T, B=one of the other columns

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Synthesis Continued By inspection,h 1i =1,h 2i =1

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Synthesis Results Next Step-To find Selector Functions that will identify the columns in which given Basis Vector appears. We look at the columns for which h 1 =1, i.e. ab=01 and ab=11, Selector Function for G 1,i.e. H 1 =b and G 2,i.e. H 2 =a; Result=f=G 1 H 1 (XOR)G 2 H 2 = bc (xor) ad;

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Multi Output Synthesis f f g g a b c d e f g f=(a+b)d (xor) abc

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Ripple Carry Adder

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Performance Considerations Some Problems with the above mentioned of merging Truth tables. >Storing a Truth Table in memory will become complex for more than 20 variables.(Increase in memory) Another Solution Proposed – Gaussian-Jordan Elimination instead of Gaussian Elimination.

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Another Efficient Approach

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FPGA Considerations Size Of LUT, used by an FPGA. INPUT KEY (SIZE OF LUT) HASH TABLE Check if LUT is created or it’s compliment Y Instead of adding New LUT, wire or inverter is added thereby saving Area N

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Modifying FLDS for Reducing Area We can Replace XOR gate by Or gate if >Product of a pair of Basis Function or their respective selector functions is zero. >Then XOR gate use to sum Basis-Selector Products can be replaced by an OR gate. 3 BASIS Functions i.e. G 1 =c, G 2 =D, G 3 =1, and it is found that selector functions for G 1 and G 2 are complements of each other and their product is 0. Therefore Unnecessary to add them using XOR.

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Experiments Technique was tested on a set of 99 MCNC benchmarks, mapping each design into a network of four input LUT’s. On the 25 of the benchmarks (classified as XOR based Logic circuits), approach provides significant area savings.

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Results-XOR Based Logic Circuits FLDS VS BDS-PGA >XOR based logic functions can be significantly reduced in size and logic depth 18.8% and 14.5% respectively FLDS VS ABC >25.3% in area and 7.7% in depth.

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Results-NON-XOR Based Logic Circuits FLDS VS ABC >ABC produces circuits with 6.2% lower area results and 16.5 lower depth.

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Future Work Proposed by Authors Both Altera and Xilinx FPGA’s contain Carry chains to implement Fast Ripple Carry Adders. These Adders contain XOR gates outside LUT’s. It is possible to utilize these XOR gate outside LUT Network to further reduce area taken by logic function.

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