Presentation is loading. Please wait.

Presentation is loading. Please wait.

Chapter 6 Digital System Design 242-208 Digital Systems and Logic Designs.

Similar presentations

Presentation on theme: "Chapter 6 Digital System Design 242-208 Digital Systems and Logic Designs."— Presentation transcript:

1 Chapter 6 Digital System Design 242-208 Digital Systems and Logic Designs

2 Content Programmable Logic Devices (PLDs) PLD programming Combinational PLDs Sequential PLDs Field programmable gate arrays (FPGAs) Systematic Design ASM methods and charts Controller and data processor designs References

3 PLD: Why we need ? Design is more economical to implement using a few Large chips than many small chips. Design and fabrication time for VLSI chips are extremely long PLD can be mage in large volume and PROGRAMMED to implement large numbers of different low-volume designs

4 What is PLD ? An IC that contains large numbers of gates, flip-flops, etc. that can be configured by the user to perform different functions Two PLD types which are : SPLD (Simple PLD) CPLSs (Complex PLD)

5 PLD programming methods: Antifuse technology Two metal layers sandwich a layer of non-conductive, amorphous silicon. When voltage is applied to this middle layer, the amorphous silicon is turned into polysilicon, which is conductive. After

6 PLD programming methods: Floating gate Used in EPROM device !! High voltage applied to the Drain, electrons jump to gate 1 Current cannot passed since no channel for carrier charge. Potential energy is still high !! UV light strikes electrons, causes more enough energy for electrons to j ump back to the channel, The transistor starts conducting !!

7 PLD programming methods: SRAM

8 Combinational PLD:PROM Programmable Read Only Memory (PROM) : A memory device that stores data at specific locations that can be addressed through a set of address pins. Another view : a large array of AND gates followed by a large array of OR gates

9 Combinational PLD:PLA Programmable Logic Array (PAL) : Both arrays of logic AND and OR are programmable

10 Combinational PLD:PAL Programmable Array Logic (PAL) consists of a programmable array of AND gates that connect to a fixed array of OR gates The PAL structure allows any SOP expression with a defined number of variables to be implemented

11 Combinational PLD:GAL A PAL that can be reprogrammed.

12 Sequential PLD: Consists of combinational PLDs with a set of FFs. See the diagram of IC PAL16R8.

13 Sequential PLD: Implement three-bit Gray code counter using PAL16R8

14 Complex PLD Programmable PLD blocks Programmable interconnects Electrically erasable links

15 Field Programmable Gate Array Why we need FPGA ? Large complex functions(millions gates) Customised design Expensive to design (in small quantities) Hard to design and long design cycles Not reprogrammable High risks Limited complexity Thousands of gates Cheap and easy to design Reprogrammable

16 Field Programmable Gate Array Why we need FPGA ? Inexpensive Easy and rapid design Prototyping Reprogrammable

17 Field Programmable Gate Array Simple programmable Logic blocks Massive of programmable interconnects FPGA architecture

18 FPGA CLB Look up table FF, registers, clock storage elements MUX CLB FPGA architecture

19 FPGA CLB with Look Up Table LUT contains memory cells to implement logic function Each cell holds ‘0’ or ‘1’ Programmed with outputs of truth table Inputs select content of one of the cells as output

20 What is in a LUT ? 4 input – 16 outputs LUT requires 16 storage elements with 16 latches.

21 FPGA CLB Larger logic functions built by connecting many CLBs together

22 Programmable routing Connections routing signals between CLBs Determined by SRAM cells

23 Programmable routing

24 Switch matrix

25 FPGA : I/O Blocks

26 Systematic Design  For circuit design:  small circuit : gate-level design (truth tables, K maps, etc)  large circuit : block-level design (ICs)  Larger digital systems need more abstract and systematic design techniques.  Systematic design methodology : Top-down approach Partitioning Developing overall architecture Detailing hardware.

27 Systematic Design : Top-down approach  Starting from original problem and gradually refine it towards solution.  Steps for a top-down design procedure: Specify the problem clearly (at global/top level without unnecessary details). Break the problem into smaller sub-problems. Repeat the process until sub-problems are small enough to be solved directly.

28 Systematic Design : Top-down approach Relevant to goal-directed approach State goal, then find sub-goals to solve main goal. Repeat until sub-goals are directly solvable.

29 Systematic Design : Partitioning A digital system consists of two components A control algorithm (Controller) An architecture (Data processor) Control unit (Controller) Data Processor (Architecture) Commands Input data External command Status condition Output data

30 ASM  Algorithmic State Machine (ASM) Chart is a high-level flowchart-like notation to specify the hardware algorithms in digital systems to obtain “control” and “data processor” units.  Major differences from flowcharts are: only three box types:- 1) state box (similar to operation box), 2) decision box 3) conditional box contains exact (or precise) timing information while flowcharts impose a relative timing order for the operations.

31 Components of ASM chart State box Rectangular shape One entry point and one exit point Used to specify one or more operations which could be simultaneously completed in one clock cycle. one or more operations state binary code

32 Components of ASM chart Decision box Diamond in shape One entry point but multiple exit points Used to specify a number of alternative paths that can be followed. deciding factors

33 Components of ASM chart Conditional box Rectangle with rounded corners Always follows a decision box and contains one or more conditional operations that are only invoked when the path containing the conditional box is selected by the decision box. conditional operations

34 Example of using ASM chart Initial state S A  0 F  0 A  A + 1 A2A2 E  0E  1 A3A3 F  1 0 0 0 1 1 1 T2T2 T1T1 T0T0 Init S=0 if S equal 1 { A = 0 F = 0 } increase A if A2 equal 1 { E =1 if A3 equal 1 { F = 1 }

35 Register operation Registers present in the data processor for storing and processing data. Flip-flops (1-bit registers) and memories (set of registers) are also considered as registers. The register operations are specified in either the state and/or conditional boxes, and are written in the form: destination register  function(other registers)

36 Timing in ASM charts Initial state S A  0 F  0 A  A + 1 A2A2 E  0E  1 A3A3 F  1 0 0 0 1 1 1 T2T2 T1T1 T0T0  Precise timing is implicitly presented in ASM charts.  Each state box, together with its immediately following decision and conditional boxes, occurs within one clock cycle.  A group of boxes which occur within a single clock cycle is called an ASM block.

37 Timing in ASM charts  Operations of ASM can be illustrated through a timing diagram.  Two factors which must be considered are operations in an ASM block occur at the same time in one clock cycle decision boxes are dependent on the status of the previous clock cycle (that is, they do not depend on operations of current block)

38 Timing in ASM charts A = A 4 A 3 A 2 A 1 Initial state S A  0 F  0 A  A + 1 A2A2 E  0E  1 A3A3 F  1 0 0 0 1 1 1 T2T2 T1T1 T0T0 Operations A0F0A0F0 A  A+1 E  0 A  A+1 E  0 A  A+1 E  1 A  A+1 E  1 A  A+1 E  0 A  A+1 E  0 A  A+1 E  1 F1F1 Operations

39 Digital system synthesis  From ASM chart, we can synthesize Controller logic (via State Table/Diagram) Architecture/Data Processor  Design of controller is determined from the decision boxes and the required state transitions.  Design requirements of data processor can be obtained from the operations specified with the state and conditional boxes.

40 Controller synthesis procedure Step 1: Identify all states and assign suitable codes. Step 2: Draw state diagram. Step 3: Formulate state table using State from state boxes Inputs from decision boxes Outputs from operations of state/conditional boxes. Step 4: Obtain state/output equations and draw circuit.

41 Controller synthesis Initial state S A  0 F  0 A  A + 1 A2A2 E  0E  1 A3A3 F  1 0 0 0 1 1 1 T2T2 T1T1 T0T0 T0T0 T1T1 T2T2 Assign codes to states: T 0 = 00 T 1 = 01 T 2 = 11 Inputs from conditions in decision boxes. Outputs = present state of controller.

42 Controller synthesis Decoder + D flip-flops -suitable for moderately large controllers. - procedure: use decoder to obtain individual states; from the state table, obtain the next- state functions by inspection.  The flip-flop input functions can be obtained directly from the state table by inspection.  This is because for the D flip-flops, the next state = flip-flop D input.  Decoder is then used to provide signals to represent different states.

43 Controller synthesis D Q D Q 2x4 decoder T0T0 T1T1 T2T2 unused G1G1 G0G0 ? ? clock  Given the state table: The inputs of the D flip-flops for G 1 and G 0 are DG 1 = T 1.A 2.A 3 DG 0 = T 0.S + T 1

44 Controller synthesis D Q D Q 2x4 decoder T0T0 T1T1 T2T2 unused G1G1 G0G0 clock A2A2 A3A3 S

45 Data processor synthesis  Architecture is more difficult to design than controller.  Nevertheless, it can be deduced from the ASM chart. In particular, the operations from the ASM chart determine: What registers to use How they can be connected What operations to support How these operations are activated.  Guidelines: always use high-level units simplest architecture possible.

46 Data processor synthesis Initial state S A  0 F  0 A  A + 1 A2A2 E  0E  1 A3A3 F  1 0 0 0 1 1 1 T2T2 T1T1 T0T0  Various operations are: Counter incremented (A  A + 1) when state = T 1. Counter cleared (A  0) when state = T 0 and S = 1. E is set (E  1) when state = T 1 and A 2 = 1. E is cleared (E  0) when state = T 1 and A 2 = 0. F is set (F  1) when state = T 2.  Deduce: One 4-bit register A (e.g.: 4-bit synchronous counter with clear/increment). Two flip-flops needed for E and F (e.g.: JK flip-flops).

47 Data processor synthesis Controller K J Q K J Q Clk 4-bit syn. counter A A2A2 A1A1 A2A2 A3A3 A3A3 A4A4 start S E F clock CP count clear T2T2 T1T1 T0T0

48 References [1] A. T. T. Choy, Lecture notes on CS1104-Computer Organization. [2] M. M. Mano, Digital Design 3 rd, Prentice-Hall. [3] John Coughlan, Lecture note on Introduction to Programmable Logic Device. [4] P. Cheung, Lecture note on Programmable Logic Devices. [5] F. Floyd, Digital Fundamentals 9 th Edition, Prentice-Hall.

Download ppt "Chapter 6 Digital System Design 242-208 Digital Systems and Logic Designs."

Similar presentations

Ads by Google