# Mohamed Younis CMCS 411, Computer Architecture 1 CMCS 411-101 Computer Architecture Lecture 7 Arithmetic Logic Unit February 19, 2001 www.csee.umbc.edu/~younis/CMSC411/

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Mohamed Younis CMCS 411, Computer Architecture 1 CMCS 411-101 Computer Architecture Lecture 7 Arithmetic Logic Unit February 19, 2001 www.csee.umbc.edu/~younis/CMSC411/ CMSC411.htm

Mohamed Younis CMCS 411, Computer Architecture 2 Lecture’s Overview q Previous Lecture: Number representation (Binary vs. decimal, Sign and magnitude, Two’s complement) Addition and Subtraction of binary numbers (Sign handling, Overflow conditions) Logical operations (Right and left shift, AND and OR) q This Lecture: Constructing an Arithmetic Logic Unit Scaling bit operations to word sizes Optimization for carry generation

Mohamed Younis CMCS 411, Computer Architecture 3 Building Blocks

Mohamed Younis CMCS 411, Computer Architecture 4 A 1-Bit Arithmetic Unit A single bit adder has 3 inputs, two operands and a carry-in and generates a sum bit and a carry-out to passed to the next 1-bit adder

Mohamed Younis CMCS 411, Computer Architecture 5 ) The multiplexor selects either a AND b, a OR b or a + b depending on whether the value of operation is 0, 1, or 2 ) To add an operation, the multiplexor has to be expanded & a circuit for performing the operation has to be appended 1-Bit logical unit A 1-Bit ALU 1-Bit adder

Mohamed Younis CMCS 411, Computer Architecture 6 Supporting Subtraction q Subtraction can be performed by inverting the operand and setting the “CarryIn” input for the adder to 1 (i.e. using two’s complement) q By adding a multiplexor to the second operand, we can select either b or b q The Binvert line indicates a subtraction operation and causes the two’s complement of b to be used as an input _ The simplicity of the hardware design of a two’s complement adder explains why it is a universal standard for computer arithmetic

Mohamed Younis CMCS 411, Computer Architecture 7 A 32-Bit ALU q A full 32-bit ALU can be created by connecting adjacent 1-bit ALU’s using the Carry in and carry out lines q The carry out of the least significant bit can ripple all the way through the adder (ripple carry adder) q Ripple carry adders are slow since the carry propagates from a unit to the next sequentially q Subtraction can be performed by inverting the operand and setting the “CarryIn” input for the whole adder to 1 (i.e. using two’s complement)

Mohamed Younis CMCS 411, Computer Architecture 8 Supporting MIPS’ “slt” instruction Most Significant Bit Basic 1-Bit ALU -Less input support the “slt instruction -“slt” produce 1 only if rs { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/13/4047228/slides/slide_8.jpg", "name": "Mohamed Younis CMCS 411, Computer Architecture 8 Supporting MIPS’ slt instruction Most Significant Bit Basic 1-Bit ALU -Less input support the slt instruction - slt produce 1 only if rs

Mohamed Younis CMCS 411, Computer Architecture 9 MIPS’ ALU Conditional Branching - “bne” and “beq” instruction compares two operands for equality - a = b iff (a-b) = 0 - Zero signal indicates all zero results ALU Symbol MIPS’ ALU Circuits

Mohamed Younis CMCS 411, Computer Architecture 10 Ripple Carry Adders q The CarryIn input depends on the operation in the adjacent 1-bit adder q The result of adding most significant bits is only available after all other bits, i.e. after n-1 single-bit additions q The sequential chain reaction is too slow to be used in time-critical hardware Carry Lookahead q Anticipate the value of the carry ahead of time q Worst-case scenario is a function of log 2 n (the number of bits in the adder) q It takes many more gates to anticipate the carry Fast Carry Using "Infinite" Hardware Using the equation: c2 = (b1. c1) + (a1. c1) + (a1. b1) c1 = (b0. c0) + (a0. c0) + (a0. b0) Substituting the definition of c1 in c2 equation c2 = (a1. a0. b0) + (a1. a0. c0) + (a1. b0. c0) + (b1. a0. b0) + (b1. a0. c0) + (b1. b0. c0) + (a1. b1) è Number of gates grows exponentially when getting to higher bits in the adder Optimizing Adder’s Design

Mohamed Younis CMCS 411, Computer Architecture 11 abc-out 000“kill” 01c-in“propagate” 10c-in“propagate” 111“generate” p = a and b g = a or b a0 b0 S a1 b1 S g p a2 b2 S a3 b3 S c-in c1 =g0 + c0  p0 c2 = g1 + g0  p1 + c0  p0  p1 c3 = g2 + g1  p2 + g0  p1  p2 + c0  p0  p1  p2 g p g p g p g p c i+1 = (b i. c i ) + (a i. c i ) + (a i. b i ) = (a i. b i ) + c i. (a i + b i ) = g i + c i. p i c i+1 = (b i. c i ) + (a i. c i ) + (a i. b i ) = (a i. b i ) + c i. (a i + b i ) = g i + c i. p i Carry Lookahead (propagate & generate) * Figure is courtesy of Dave Patterson

Mohamed Younis CMCS 411, Computer Architecture 12 Plumbing as Carry Lookahead Analogy The pipe will output water if one of the wrenches is turned to open a valve

Mohamed Younis CMCS 411, Computer Architecture 14 An Example Determine g i, p i, P i, G i and carry out (C 4 ) values for these two 16-bit numbers: a:0001 1010 0011 0011 b:1110 0101 1110 1011 Answer: Using the formula g i = (a i. b i ) and p i = (a i + b i ) g i :0000 0000 0010 0011 p i :1111 1111 1111 1011 The “super” propagates (P 0, P 1, P 2, P 3 ) are calculated as follows: P 0 = p 3. p 2. p 1. p 0 = 0 P 1 = p 7. p 6. p 5. p 4 = 1 P 2 = p 11. p 10. p 9. p 8 = 1 P 3 = p 15. p 14. p 13. p 12 = 1 The “super” generates (G 0, G 1, G 2, G 3 ) are calculated as follows: G 0 = g 3 + (p 3.g 2 ) + (p 3.p 2.g 1 ) + (p 3.p 2.p 1.g 0 ) = 0 G 1 = g 7 + (p 7.g 6 ) + (p 7.p 6.g 5 ) + (p 7.p 6.p 5.g 4 ) = 1 G 2 = g 11 + (p 11.g 10 ) + (p 11.p 10.g 9 ) + (p 11.p 10.p 9.g 8 ) = 0 G 3 = g 15 + (p 15.g 14 ) + (p 15.p 14.g 13 ) + (p 15.p 14.g 13.g 12 ) = 0 Finally carry-out (C 4 ) is: C 4 = G 3 + (P 3.G 2 ) + (P 3.P 2.G 1 ) + (P 3.P 2.P 1.G 0 ) + (P 3.P 2.P 1.P 0.C 0 ) = 1

Mohamed Younis CMCS 411, Computer Architecture 15 Speed of Carry Generation It takes two gates delay for carry-out to be available in a single bit adder q There is a (gate) delay for an output to be ready once input signals are applied to a gate q Time is estimated by simply counting the number of gates along the longest path q Carry lookahead is faster because less cascaded levels of logic gates are used q For a 16-bit ripple carry adder, carry-out is subject to 32 (16  2 for 1 -bit adder) gate q Cascaded carry lookahead (C4) is delayed by only 5 gates (1 for p and g, 2 for G and 2 for C4) in a 16-bit adder

Mohamed Younis CMCS 411, Computer Architecture 16 Conclusion q Summary è Constructing an Arithmetic Logic Unit (Different blocks and gluing them together) è Scaling bit operations to word sizes (Ripple carry adder, MIPS ALU) è Optimization for carry handling (Measuring performance, Carry lookahead) q Next Lecture è Design phases è Hardware design languages (HDL) è The “eSim” miniaturized HDL Reading assignment is section 4.5 in text book

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