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© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

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© Digital Integrated Circuits 2nd Inverter DIGITAL GATES Fundamental Parameters Functionality Reliability, Robustness Area Performance DC Characteristics Speed (delay) Power Consumption

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© Digital Integrated Circuits 2nd Inverter Noise in Digital Integrated Circuits

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© Digital Integrated Circuits 2nd Inverter The Ideal Gate

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V M = f(R n, R p ) V DD V V in = V DD V in = 0 V out V R n R p

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© Digital Integrated Circuits 2nd Inverter Mapping between analog and digital signals

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© Digital Integrated Circuits 2nd Inverter Definition of Noise Margins

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© Digital Integrated Circuits 2nd Inverter The Regenerative Property

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© Digital Integrated Circuits 2nd Inverter Fan-in and Fan-out

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© Digital Integrated Circuits 2nd Inverter The CMOS Inverter: A First Glance V in V out C L V DD

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

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© Digital Integrated Circuits 2nd Inverter VTC of Real Inverter

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Transient Response t pHL = f(R on.C L ) = 0.69 R on C L V out V R n R p V DD V V in = V DD V in = 0 (a) Low-to-high(b) High-to-low C L C L

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© Digital Integrated Circuits 2nd Inverter Delay Definitions

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© Digital Integrated Circuits 2nd Inverter Ring Oscillator

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© Digital Integrated Circuits 2nd Inverter Power Dissipation

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© Digital Integrated Circuits 2nd Inverter Voltage Transfer Characteristic

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

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© Digital Integrated Circuits 2nd Inverter DC Operation: Voltage Transfer Characteristic V(x) V(y) V OH V OL V LT V OH V OL f V(y)=V(x) Switching Logic Threshold Nominal Voltage Levels V(y)V(x) VIL VIH dVo/dVi =-1 NML NMH

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Load Characteristics I n,p V in = 5 V in = 4 V in = 3 V in = 0 V in = 1 V in = 2 NMOS PMOS V in = 0 V in = 1 V in = 2 V in = 3 V in = 4 V in = 4 V in = 5 V in = 2 V in = 3 Vout

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC Vin < Vtn -NMOS Off Vin > Vdd – Vtp -PMOS Off PMOS: linear if Vsg –Vtp > Vsd Vo > Vin +Vtp NMOS: Linear if Vgs-Vtn > Vds Vo < Vin –Vtn VOH: PMOS(lin) & NMOS(off) VOL: PMOS(off) & NMOS(lin) VIH: PMOS(sat) & NMOS(lin) VIL: PMOS(lin) & NMOS(sat) VLT: PMOS(sat) & NMOS(sat)

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC VOH: PMOS(lin) & NMOS(off) = Vdd VOL: PMOS(off) & NMOS(lin) = Gnd VIH: PMOS(sat) & NMOS(lin): Solve: VIL: PMOS(lin) & NMOS(sat): Solve:

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC VLT: PMOS(sat) & NMOS(sat): If Vtn = Vtp & p = n VLT = Vdd/2: Gives a symmetric Inverter!

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© Digital Integrated Circuits 2nd Inverter Simulated VTC

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© Digital Integrated Circuits 2nd Inverter Gate Logic Switching Threshold p // n V LT

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© Digital Integrated Circuits 2nd Inverter Inverter Gain

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© Digital Integrated Circuits 2nd Inverter Gain as a function of VDD Gain=-1

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© Digital Integrated Circuits 2nd Inverter Impact of Process Variations V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal

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© Digital Integrated Circuits 2nd Inverter Propagation Delay

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© Digital Integrated Circuits 2nd Inverter Delay Definitions

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter: Transient Response

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay V DD V out V in = V DD C L I av t pHL = C L V swing /2 I av C L k n V DD ~

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay V DD V out V in = V DD C L Vdd Vo Time VH Vdd-Vtn to t1 t2 VL NMOS(sat) NMOS(lin)

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay Similarly:

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© Digital Integrated Circuits 2nd Inverter CMOS Inverter Rise & Fall Time Similarly, Rise Time: Similarly, Fall Time:

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© Digital Integrated Circuits 2nd Inverter Computing the Capacitances

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© Digital Integrated Circuits 2nd Inverter CMOS Inverters Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2 m =2

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© Digital Integrated Circuits 2nd Inverter The Miller Effect

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© Digital Integrated Circuits 2nd Inverter Computing the Capacitances

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© Digital Integrated Circuits 2nd Inverter Impact of Rise Time on Delay

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© Digital Integrated Circuits 2nd Inverter Delay as a function of V DD

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© Digital Integrated Circuits 2nd Inverter NMOS/PMOS ratio tpLH tpHL tp = W p /W n

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© Digital Integrated Circuits 2nd Inverter Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

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© Digital Integrated Circuits 2nd Inverter Design for Performance Keep capacitances small Increase transistor sizes watch out for self-loading! Increase V DD (????)

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© Digital Integrated Circuits 2nd Inverter Impact of Rise Time on Delay

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© Digital Integrated Circuits 2nd Inverter Inverter Sizing

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© Digital Integrated Circuits 2nd Inverter Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

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© Digital Integrated Circuits 2nd Inverter Inverter Delay Minimum length devices, L=0.7 m Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2W2W W Load for the next stage:

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© Digital Integrated Circuits 2nd Inverter Inverter with Load Load (C L ) Delay Assumptions: no load -> zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

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© Digital Integrated Circuits 2nd Inverter Inverter with Load Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int + kR W C L = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2C unit 2W2W W

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© Digital Integrated Circuits 2nd Inverter Delay Formula C int = C gin with 1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

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© Digital Integrated Circuits 2nd Inverter Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

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© Digital Integrated Circuits 2nd Inverter Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

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© Digital Integrated Circuits 2nd Inverter Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

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© Digital Integrated Circuits 2nd Inverter Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

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© Digital Integrated Circuits 2nd Inverter Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For = 0, f = e, N = lnF

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© Digital Integrated Circuits 2nd Inverter Optimum Effective Fanout f Optimum f for given process defined by f opt = 3.6 for =1

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© Digital Integrated Circuits 2nd Inverter Impact of Self-Loading on tp No Self-Loading, =0 With Self-Loading =1

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© Digital Integrated Circuits 2nd Inverter Normalized delay function of F

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© Digital Integrated Circuits 2nd Inverter Buffer Design Nft p

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© Digital Integrated Circuits 2nd Inverter Power Dissipation

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© Digital Integrated Circuits 2nd Inverter Where Does Power Go in CMOS?

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© Digital Integrated Circuits 2nd Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

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© Digital Integrated Circuits 2nd Inverter Modification for Circuits with Reduced Swing

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© Digital Integrated Circuits 2nd Inverter Adiabatic Charging 2 2 2

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© Digital Integrated Circuits 2nd Inverter Adiabatic Charging

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© Digital Integrated Circuits 2nd Inverter Node Transition Activity and Power

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© Digital Integrated Circuits 2nd Inverter Short Circuit Currents

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© Digital Integrated Circuits 2nd Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

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© Digital Integrated Circuits 2nd Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

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© Digital Integrated Circuits 2nd Inverter Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

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© Digital Integrated Circuits 2nd Inverter Reverse-Biased Diode Leakage JS = pA/ m2 at 25 deg C for 0.25 m CMOS JS doubles for every 9 deg C!

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© Digital Integrated Circuits 2nd Inverter Subthreshold Leakage Component

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© Digital Integrated Circuits 2nd Inverter Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

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© Digital Integrated Circuits 2nd Inverter Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 … 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47

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© Digital Integrated Circuits 2nd Inverter Impact of Technology Scaling

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© Digital Integrated Circuits 2nd Inverter Goals of Technology Scaling Make things cheaper: Want to sell more functions (transistors) per chip for the same money Build same products cheaper, sell the same part for less money Price of a transistor has to be reduced But also want to be faster, smaller, lower power

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© Digital Integrated Circuits 2nd Inverter Technology Scaling Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power 43% increase in frequency Die size used to increase by 14% per generation Technology generation spans 2-3 years

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© Digital Integrated Circuits 2nd Inverter Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Max P power [W] Max frequency [GHz],Local-Global Bat. power [W] Wiring levels Supply [V] Technology node [nm] Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

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© Digital Integrated Circuits 2nd Inverter ITRS Technology Roadmap Acceleration Continues

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© Digital Integrated Circuits 2nd Inverter Technology Scaling (1) Minimum Feature Size

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© Digital Integrated Circuits 2nd Inverter Technology Scaling (2) Number of components per chip

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© Digital Integrated Circuits 2nd Inverter Technology Scaling (3) Propagation Delay t p decreases by 13%/year 50% every 5 years!

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© Digital Integrated Circuits 2nd Inverter Technology Scaling (4) From Kuroda

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© Digital Integrated Circuits 2nd Inverter Technology Scaling Models

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© Digital Integrated Circuits 2nd Inverter Scaling Relationships for Long Channel Devices

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© Digital Integrated Circuits 2nd Inverter Transistor Scaling (velocity-saturated devices)

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© Digital Integrated Circuits 2nd Inverter Processor Scaling P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter Processor Power P. Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter Processor Performance P. Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter 2010 Outlook Performance 2X/16 months 1 TIP (terra instructions/s) 30 GHz clock Size No of transistors: 2 Billion Die: 40*40 mm Power 10kW!! Leakage: 1/3 active Power P.Gelsinger: Processors for the New Millenium, ISSCC 2001

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© Digital Integrated Circuits 2nd Inverter Some interesting questions What will cause this model to break? When will it break? Will the model gradually slow down? Power and power density Leakage Process Variation

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