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© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

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Presentation on theme: "© Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic."— Presentation transcript:

1 © Digital Integrated Circuits 2nd Inverter Digital Integrated Circuits A Design Perspective The Inverter Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic

2 © Digital Integrated Circuits 2nd Inverter DIGITAL GATES Fundamental Parameters  Functionality  Reliability, Robustness  Area  Performance  DC Characteristics  Speed (delay)  Power Consumption

3 © Digital Integrated Circuits 2nd Inverter Noise in Digital Integrated Circuits

4 © Digital Integrated Circuits 2nd Inverter The Ideal Gate

5 © Digital Integrated Circuits 2nd Inverter CMOS Inverter First-Order DC Analysis V OL = 0 V OH = V DD V M = f(R n, R p ) V DD V V in = V DD V in = 0 V out V R n R p

6 © Digital Integrated Circuits 2nd Inverter Mapping between analog and digital signals

7 © Digital Integrated Circuits 2nd Inverter Definition of Noise Margins

8 © Digital Integrated Circuits 2nd Inverter The Regenerative Property

9 © Digital Integrated Circuits 2nd Inverter Fan-in and Fan-out

10 © Digital Integrated Circuits 2nd Inverter The CMOS Inverter: A First Glance V in V out C L V DD

11 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

12 © Digital Integrated Circuits 2nd Inverter VTC of Real Inverter

13 © Digital Integrated Circuits 2nd Inverter CMOS Inverter: Transient Response t pHL = f(R on.C L ) = 0.69 R on C L V out V R n R p V DD V V in = V DD V in = 0 (a) Low-to-high(b) High-to-low C L C L

14 © Digital Integrated Circuits 2nd Inverter Delay Definitions

15 © Digital Integrated Circuits 2nd Inverter Ring Oscillator

16 © Digital Integrated Circuits 2nd Inverter Power Dissipation

17 © Digital Integrated Circuits 2nd Inverter Voltage Transfer Characteristic

18 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Polysilicon In Out V DD GND PMOS 2 Metal 1 NMOS Contacts N Well

19 © Digital Integrated Circuits 2nd Inverter DC Operation: Voltage Transfer Characteristic V(x) V(y) V OH V OL V LT V OH V OL f V(y)=V(x) Switching Logic Threshold Nominal Voltage Levels V(y)V(x) VIL VIH dVo/dVi =-1 NML NMH

20 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Load Characteristics I n,p V in = 5 V in = 4 V in = 3 V in = 0 V in = 1 V in = 2 NMOS PMOS V in = 0 V in = 1 V in = 2 V in = 3 V in = 4 V in = 4 V in = 5 V in = 2 V in = 3 Vout

21 © Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC Vin < Vtn -NMOS Off Vin > Vdd – Vtp -PMOS Off PMOS: linear if Vsg –Vtp > Vsd Vo > Vin +Vtp NMOS: Linear if Vgs-Vtn > Vds Vo < Vin –Vtn VOH: PMOS(lin) & NMOS(off) VOL: PMOS(off) & NMOS(lin) VIH: PMOS(sat) & NMOS(lin) VIL: PMOS(lin) & NMOS(sat) VLT: PMOS(sat) & NMOS(sat)

22 © Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC VOH: PMOS(lin) & NMOS(off) = Vdd VOL: PMOS(off) & NMOS(lin) = Gnd VIH: PMOS(sat) & NMOS(lin): Solve: VIL: PMOS(lin) & NMOS(sat): Solve:

23 © Digital Integrated Circuits 2nd Inverter CMOS Inverter VTC VLT: PMOS(sat) & NMOS(sat): If Vtn = Vtp &  p =  n  VLT = Vdd/2: Gives a symmetric Inverter!

24 © Digital Integrated Circuits 2nd Inverter Simulated VTC

25 © Digital Integrated Circuits 2nd Inverter Gate Logic Switching Threshold  p // n V LT

26 © Digital Integrated Circuits 2nd Inverter Inverter Gain

27 © Digital Integrated Circuits 2nd Inverter Gain as a function of VDD Gain=-1

28 © Digital Integrated Circuits 2nd Inverter Impact of Process Variations V in (V) V out (V) Good PMOS Bad NMOS Good NMOS Bad PMOS Nominal

29 © Digital Integrated Circuits 2nd Inverter Propagation Delay

30 © Digital Integrated Circuits 2nd Inverter Delay Definitions

31 © Digital Integrated Circuits 2nd Inverter CMOS Inverter: Transient Response

32 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay V DD V out V in = V DD C L I av t pHL = C L V swing /2 I av C L k n V DD ~

33 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay V DD V out V in = V DD C L Vdd Vo Time VH Vdd-Vtn to t1 t2 VL NMOS(sat) NMOS(lin)

34 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Propagation Delay Similarly:

35 © Digital Integrated Circuits 2nd Inverter CMOS Inverter Rise & Fall Time Similarly, Rise Time: Similarly, Fall Time:

36 © Digital Integrated Circuits 2nd Inverter Computing the Capacitances

37 © Digital Integrated Circuits 2nd Inverter CMOS Inverters Polysilicon In Out Metal1 V DD GND PMOS NMOS 1.2  m =2

38 © Digital Integrated Circuits 2nd Inverter The Miller Effect

39 © Digital Integrated Circuits 2nd Inverter Computing the Capacitances

40 © Digital Integrated Circuits 2nd Inverter Impact of Rise Time on Delay

41 © Digital Integrated Circuits 2nd Inverter Delay as a function of V DD

42 © Digital Integrated Circuits 2nd Inverter NMOS/PMOS ratio tpLH tpHL tp  = W p /W n

43 © Digital Integrated Circuits 2nd Inverter Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

44 © Digital Integrated Circuits 2nd Inverter Design for Performance  Keep capacitances small  Increase transistor sizes  watch out for self-loading!  Increase V DD (????)

45 © Digital Integrated Circuits 2nd Inverter Impact of Rise Time on Delay

46 © Digital Integrated Circuits 2nd Inverter Inverter Sizing

47 © Digital Integrated Circuits 2nd Inverter Inverter Chain CLCL If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters? May need some additional constraints. In Out

48 © Digital Integrated Circuits 2nd Inverter Inverter Delay Minimum length devices, L=0.7  m Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2W2W W Load for the next stage:

49 © Digital Integrated Circuits 2nd Inverter Inverter with Load Load (C L ) Delay Assumptions: no load -> zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

50 © Digital Integrated Circuits 2nd Inverter Inverter with Load Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int + kR W C L = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2C unit 2W2W W

51 © Digital Integrated Circuits 2nd Inverter Delay Formula C int =  C gin with   1 f = C L /C gin - effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit

52 © Digital Integrated Circuits 2nd Inverter Apply to Inverter Chain CLCL InOut 12N t p = t p1 + t p2 + …+ t pN

53 © Digital Integrated Circuits 2nd Inverter Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 – C gin,N Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors - each stage has the same effective fanout (C out /C in ) - each stage has the same delay

54 © Digital Integrated Circuits 2nd Inverter Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Minimum path delay Effective fanout of each stage:

55 © Digital Integrated Circuits 2nd Inverter Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages:

56 © Digital Integrated Circuits 2nd Inverter Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For  = 0, f = e, N = lnF

57 © Digital Integrated Circuits 2nd Inverter Optimum Effective Fanout f Optimum f for given process defined by  f opt = 3.6 for  =1

58 © Digital Integrated Circuits 2nd Inverter Impact of Self-Loading on tp No Self-Loading,  =0 With Self-Loading  =1

59 © Digital Integrated Circuits 2nd Inverter Normalized delay function of F

60 © Digital Integrated Circuits 2nd Inverter Buffer Design Nft p

61 © Digital Integrated Circuits 2nd Inverter Power Dissipation

62 © Digital Integrated Circuits 2nd Inverter Where Does Power Go in CMOS?

63 © Digital Integrated Circuits 2nd Inverter Dynamic Power Dissipation Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. VinVout C L Vdd Not a function of transistor sizes!

64 © Digital Integrated Circuits 2nd Inverter Modification for Circuits with Reduced Swing

65 © Digital Integrated Circuits 2nd Inverter Adiabatic Charging 2 2 2

66 © Digital Integrated Circuits 2nd Inverter Adiabatic Charging

67 © Digital Integrated Circuits 2nd Inverter Node Transition Activity and Power

68 © Digital Integrated Circuits 2nd Inverter Short Circuit Currents

69 © Digital Integrated Circuits 2nd Inverter How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can’t do this for cascade logic, so...

70 © Digital Integrated Circuits 2nd Inverter Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3

71 © Digital Integrated Circuits 2nd Inverter Leakage Sub-threshold current one of most compelling issues in low-energy circuit design!

72 © Digital Integrated Circuits 2nd Inverter Reverse-Biased Diode Leakage JS = pA/  m2 at 25 deg C for 0.25  m CMOS JS doubles for every 9 deg C!

73 © Digital Integrated Circuits 2nd Inverter Subthreshold Leakage Component

74 © Digital Integrated Circuits 2nd Inverter Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

75 © Digital Integrated Circuits 2nd Inverter Principles for Power Reduction  Prime choice: Reduce voltage!  Recent years have seen an acceleration in supply voltage reduction  Design at very low voltages still open question (0.6 … 0.9 V by 2010!)  Reduce switching activity  Reduce physical capacitance  Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47

76 © Digital Integrated Circuits 2nd Inverter Impact of Technology Scaling

77 © Digital Integrated Circuits 2nd Inverter Goals of Technology Scaling  Make things cheaper:  Want to sell more functions (transistors) per chip for the same money  Build same products cheaper, sell the same part for less money  Price of a transistor has to be reduced  But also want to be faster, smaller, lower power

78 © Digital Integrated Circuits 2nd Inverter Technology Scaling  Goals of scaling the dimensions by 30%:  Reduce gate delay by 30% (increase operating frequency by 43%)  Double transistor density  Reduce energy per transition by 65% (50% power 43% increase in frequency  Die size used to increase by 14% per generation  Technology generation spans 2-3 years

79 © Digital Integrated Circuits 2nd Inverter Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Max  P power [W] Max frequency [GHz],Local-Global Bat. power [W] Wiring levels Supply [V] Technology node [nm] Year of Introduction Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

80 © Digital Integrated Circuits 2nd Inverter ITRS Technology Roadmap Acceleration Continues

81 © Digital Integrated Circuits 2nd Inverter Technology Scaling (1) Minimum Feature Size

82 © Digital Integrated Circuits 2nd Inverter Technology Scaling (2) Number of components per chip

83 © Digital Integrated Circuits 2nd Inverter Technology Scaling (3) Propagation Delay t p decreases by 13%/year 50% every 5 years!

84 © Digital Integrated Circuits 2nd Inverter Technology Scaling (4) From Kuroda

85 © Digital Integrated Circuits 2nd Inverter Technology Scaling Models

86 © Digital Integrated Circuits 2nd Inverter Scaling Relationships for Long Channel Devices

87 © Digital Integrated Circuits 2nd Inverter Transistor Scaling (velocity-saturated devices)

88 © Digital Integrated Circuits 2nd Inverter  Processor Scaling P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

89 © Digital Integrated Circuits 2nd Inverter  Processor Power P. Gelsinger:  Processors for the New Millenium, ISSCC 2001

90 © Digital Integrated Circuits 2nd Inverter  Processor Performance P. Gelsinger:  Processors for the New Millenium, ISSCC 2001

91 © Digital Integrated Circuits 2nd Inverter 2010 Outlook  Performance 2X/16 months  1 TIP (terra instructions/s)  30 GHz clock  Size  No of transistors: 2 Billion  Die: 40*40 mm  Power  10kW!!  Leakage: 1/3 active Power P.Gelsinger:  Processors for the New Millenium, ISSCC 2001

92 © Digital Integrated Circuits 2nd Inverter Some interesting questions  What will cause this model to break?  When will it break?  Will the model gradually slow down?  Power and power density  Leakage  Process Variation


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