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©UCB CPSC 161 Lecture 6 Prof. L.N. Bhuyan
©UCB °Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers °Binary numbers (base 2) decimal: n -1 °Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number °How do we represent negative numbers? i.e., which bit patterns will represent which numbers? Numbers
©UCB ° Sign Magnitude: One's Complement Two's Complement 000 = = = = = = = = = = = = = = = = = = = = = = = = -1 °Issues: balance, number of zeros, ease of operations °Which one is best? Why? Possible Representations
©UCB °32 bit signed numbers: two = 0 ten two = + 1 ten two = + 2 ten two = + 2,147,483,646 ten two = + 2,147,483,647 ten two = – 2,147,483,648 ten two = – 2,147,483,647 ten two = – 2,147,483,646 ten two = – 3 ten two = – 2 ten two = – 1 ten maxint minint MIPS
©UCB °Negating a two's complement number: invert all bits and add 1 remember: “negate” and “invert” are quite different! °Converting n bit numbers into numbers with more than n bits: MIPS 16 bit immediate gets converted to 32 bits for arithmetic copy the most significant bit (the sign bit) into the other bits > > "sign extension" (lbu vs. lb) Two's Complement Operations
©UCB °Just like in grade school (carry/borrow 1s) °Two's complement operations easy subtraction using addition of negative numbers °Overflow (result too large for finite computer word): e.g., adding two n-bit numbers does not yield an n-bit number note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed” Addition & Subtraction
©UCB MIPS ALU Instructions °Add, AddU, Sub, SubU, AddI, AddIU => 2’s complement adder/sub with overflow detection °And, Or, AndI, OrI, Xor, Xori, Nor => Logical AND, logical OR, XOR, nor °SLTI, SLTIU (set less than) => 2’s complement adder with inverter, check sign bit of result
©UCB MIPS arithmetic instruction format R-type: I-Type: opRsRtRdfunct opRsRtImmed 16 Typeopfunct ADDI10xx ADDIU11xx SLTI12xx SLTIU13xx ANDI14xx ORI15xx XORI16xx LUI17xx Typeopfunct ADD0040 ADDU0041 SUB0042 SUBU0043 AND0044 OR0045 XOR0046 NOR0047 Typeopfunct SLT0052 SLTU0053
©UCB Refined Requirements (1) Functional Specification inputs: 2 x 32-bit operands A, B, 4-bit mode outputs:32-bit result S, 1-bit carry, 1 bit overflow operations:add, addu, sub, subu, and, or, xor, nor, slt, sltU (2) Block Diagram ALU AB m ovf S 32 4 c
©UCB Refined Diagram: bit-slice ALU °Co = a.b + a.Cin + b.Cin °Sum = AB M S 32 4 Ovflw ALU0 a0b0 m cinco s0 ALU0 a31b31 m cinco s31
©UCB Seven plus a MUX ? A B 1-bit Full Adder CarryOut Mux CarryIn Result °Design trick 2: take pieces you know (or can imagine) and try to put them together °Design trick 3: solve part of the problem and extend add and or S-select
©UCB Additional operations °A - B = A + (– B) form two complement by invert and add one A B 1-bit Full Adder CarryOut Mux CarryIn Result add and or S-select invert Set-less-than? – left as an exercise
©UCB °No overflow when adding a positive and a negative number °No overflow when signs are the same for subtraction °Overflow occurs when the value affects the sign: overflow when adding two positives yields a negative or, adding two negatives gives a positive or, subtract a negative from a positive and get a negative or, subtract a positive from a negative and get a positive °Consider the operations A + B, and A – B Can overflow occur if B is 0 ? Can overflow occur if A is 0 ? Detecting Overflow
©UCB °An exception (interrupt) occurs Control jumps to predefined address for exception Interrupted address is saved for possible resumption °Details based on software system / language example: flight control vs. homework assignment °Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons Effects of Overflow
©UCB Overflow Detection °Overflow: the result is too large (or too small) to represent properly Example: - 8 < = 4-bit binary number <= 7 °When adding operands with different signs, overflow cannot occur! °Overflow occurs when adding: 2 positive numbers and the sum is negative 2 negative numbers and the sum is positive °On your own: Prove you can detect overflow by: Carry into MSB ° Carry out of MSB – 6 –4 – 5 7 0
©UCB Overflow Detection Logic °Carry into MSB ° Carry out of MSB For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1] A0 B0 1-bit ALU Result0 CarryIn0 CarryOut0 A1 B1 1-bit ALU Result1 CarryIn1 CarryOut1 A2 B2 1-bit ALU Result2 CarryIn2 A3 B3 1-bit ALU Result3 CarryIn3 CarryOut3 Overflow XYX XOR Y
©UCB But What about Performance? °Critical Path of n-bit Rippled-carry adder is n*CP A0 B0 1-bit ALU Result0 CarryIn0 CarryOut0 A1 B1 1-bit ALU Result1 CarryIn1 CarryOut1 A2 B2 1-bit ALU Result2 CarryIn2 CarryOut2 A3 B3 1-bit ALU Result3 CarryIn3 CarryOut3 Design Trick: throw hardware at it
©UCB Carry Look Ahead (Design trick: peek) ABC-out 000“kill” 01C-in“propagate” 10C-in“propagate” 111“generate” A0 B1 S G P P = A and B G = A xor B A B S G P A B S G P A B S G P Cin C1 =G0 + C0 P0 C2 = G1 + G0 P1 + C0 P0 P1 C3 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2 G C4 =... P
©UCB Cascaded Carry Look-ahead (16-bit): Abstraction CLACLA 4-bit Adder 4-bit Adder 4-bit Adder C1 =G0 + C0 P0 C2 = G1 + G0 P1 + C0 P0 P1 C3 = G2 + G1 P2 + G0 P1 P2 + C0 P0 P1 P2 G P G0 P0 C4 =... C0
©UCB Additional MIPS ALU requirements °Mult, MultU, Div, DivU (next lecture) => Need 32-bit multiply and divide, signed and unsigned °Sll, Srl, Sra (next lecture) => Need left shift, right shift, right shift arithmetic by 0 to 31 bits °Nor (leave as exercise to reader) => logical NOR or use 2 steps: (A OR B) XOR
©UCB °More complicated than addition accomplished via shifting and addition °More time and more area °Let's look at 3 versions based on a gradeschool algorithm 0010 (multiplicand) __x_1011 (multiplier) °Negative numbers: convert and multiply there are better techniques, we won’t look at them Multiplication
©UCB Multiplication: Implementation Datapath Control
©UCB Final Version What goes here? Multiplier starts in right half of product
©UCB Floating Point (a brief look) °We need a way to represent numbers with fractions, e.g., very small numbers, e.g., very large numbers, e.g., 10 9 °Representation: sign, exponent, significand: (–1) sign significand 2 exponent more bits for significand gives more accuracy more bits for exponent increases range °IEEE 754 floating point standard: single precision: 8 bit exponent, 23 bit significand double precision: 11 bit exponent, 52 bit significand
©UCB IEEE 754 floating-point standard °Leading “1” bit of significand is implicit °Exponent is “biased” to make sorting easier all 0s is smallest exponent all 1s is largest bias of 127 for single precision and 1023 for double precision summary: (–1) sign significand) 2 exponent – bias °Example: decimal: -.75 = - ( ½ + ¼ ) binary: -.11 = -1.1 x 2 -1 floating point: exponent = 126 = IEEE single precision:
©UCB Floating point addition °
©UCB Floating Point Complexities °Operations are more complicated (see text) °In addition to overflow we can have “underflow” °Accuracy can be a big problem IEEE 754 keeps two extra bits, guard and round four rounding modes positive divided by zero yields “infinity” zero divide by zero yields “not a number” other complexities °Implementing the standard can be tricky °Not using the standard can be even worse see text for description of 80x86 and Pentium bug!
©UCB Chapter Three Summary °Computer arithmetic is constrained by limited precision °Bit patterns have no inherent meaning but standards do exist two’s complement IEEE 754 floating point °Computer instructions determine “meaning” of the bit patterns °Performance and accuracy are important so there are many complexities in real machines °Algorithm choice is important and may lead to hardware optimizations for both space and time (e.g., multiplication) °You may want to look back (Section 3.10 is great reading!)
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