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© 2012 VMware Inc. All rights reserved CPU and Memory Virtualization Prashanth Bungale, Sr. Member of Technical Staff, Mobile Virtualization January 23.

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Presentation on theme: "© 2012 VMware Inc. All rights reserved CPU and Memory Virtualization Prashanth Bungale, Sr. Member of Technical Staff, Mobile Virtualization January 23."— Presentation transcript:

1 © 2012 VMware Inc. All rights reserved CPU and Memory Virtualization Prashanth Bungale, Sr. Member of Technical Staff, Mobile Virtualization January 23 rd 2012 Sponsored by MIT and VMware Academic Programs VMware: VMware Labs: labs.vmware.com

2 2 Why Virtualize?  Server Consolidation Convert underutilized servers to VMs Significant cost savings (equipment, space, power) Increasingly used for virtual desktops  Simplified Management Datacenter provisioning and monitoring Dynamic load balancing  Improved Availability Automatic restart Fault tolerance Disaster recovery  Test and Development  Mobile Virtualization Home/Work Dual Persona

3 3 Overview  CPU Background  Virtualization and VMs  CPU Virtualization  Memory Virtualization

4 4 Computer System Organization NIC LA N CPU MMU Memory Controller Local Bus Interface High-Speed I/O Bus ControllerBridge Frame Buffer Low-Speed I/O Bus USBCD-ROM

5 5 CPU Organization  Instruction Set Architecture (ISA) Defines: the state visible to the programmer registers and memory the instruction that operate on the state  ISA typically divided into 2 parts User ISA Primarily for computation System ISA Primarily for system resource management

6 6 User ISA - State User Virtual Memory Program Counter Condition Codes Reg 0 Reg 1 Reg n-1 FP 0 FP 1 FP n-1 Special-Purpose Registers General-Purpose Registers Floating Point Registers

7 7 System ISA  Privilege Levels  Control Registers  Traps and Interrupts Hardcoded Vectors Dispatch Table  System Clock  MMU Page Tables TLB  I/O Device Access System User Extension Kernel Level 0 Level 1 Level 2

8 8 Types of Virtualization  Process Virtualization Language-level Java,.NET, Smalltalk OS-level processes, Solaris Zones, BSD Jails, Virtuozzo Cross-ISA emulation Apple 68K-PPC-x86, Digital FX!32  Device Virtualization Logical vs. physical VLAN, VPN, NPIV, LUN, RAID  System Virtualization “Hosted” VMware Workstation, Microsoft VPC, Parallels “Bare metal” VMware ESX, Xen, Microsoft Hyper-V

9 9 Starting Point: A Physical Machine  Physical Hardware Processors, memory, chipset, I/O devices, etc. Resources often grossly underutilized  Software Tightly coupled to physical hardware Single active OS instance OS controls hardware

10 10 What is a Virtual Machine?  Software Abstraction Behaves like hardware Encapsulates all OS and application state  Virtualization Layer Extra level of indirection Decouples hardware, OS Enforces isolation Multiplexes physical hardware across VMs

11 11 Virtualization Properties  Isolation Fault isolation Performance isolation  Encapsulation Cleanly capture all VM state Enables VM snapshots, clones  Portability Independent of physical hardware Enables migration of live, running VMs  Interposition Transformations on instructions, memory, I/O Enables transparent resource overcommitment, encryption, compression, replication …

12 12 What is a Virtual Machine Monitor?  Classic Definition (Popek and Goldberg ’74)  VMM Properties Fidelity Performance Safety and Isolation

13 13 Overview  CPU Background  Virtualization and VMs  CPU Virtualization System ISA Virtualization Instruction Interpretation Trap and Emulate Binary Translation Para-Virtualization Hardware Assisted Virtualization  Memory Virtualization

14 14 Virtualizing the System ISA  Hardware needed by monitor Ex: monitor must control real hardware interrupts  Access to hardware would allow VM to compromise isolation boundaries Ex: access to MMU would allow VM to write any page  So… All access to the virtual System ISA by the guest must be emulated by the monitor in software. System state kept in memory. System instructions are implemented as functions in the monitor.

15 15 Instruction Interpretation  Emulate Fetch/Decode/Execute pipeline in software  Postives Easy to implement Minimal complexity  Negatives Slow!

16 16 Trap and Emulate Guest OS + Applications Virtual Machine Monitor Page Fault Undef Instr vIRQ MMU Emulation CPU Emulation I/O Emulation Unprivileged Privileged

17 17 “Strictly Virtualizable” A processor or mode of a processor is strictly virtualizable if, when executed in a lesser privileged mode:  all instructions that access privileged state trap  all instructions either trap or execute identically

18 18 Issues with Trap and Emulate  Not all architectures support it  Trap costs may be high  VMM consumes a privilege level Need to virtualize the protection levels

19 19 Binary Translation vPC mov ebx, eax cli and ebx, ~0xfff mov ebx, cr3 sti ret mov ebx, eax mov [CPU_IE], 0 and ebx, ~0xfff mov [CO_ARG], ebx call HANDLE_CR3 mov [CPU_IE], 1 test [CPU_IRQ], 1 jne call HANDLE_INTS jmp HANDLE_RET start Guest CodeTranslation Cache

20 20 Issues with Binary Translation  Translation cache management  PC synchronization on interrupts  Self-modifying code Notified on writes to translated guest code  Protecting VMM from guest

21 21 Other Uses for Binary Translation  Cross ISA translators Apple’s Rosetta – PowePC to Intel, Digital FX!32  Optimizing translators HP Dynamo  High level language byte code translators Java.NET/CLI

22 22 Para-Virtualization  Key idea: present a software interface to VM’s that is similar but not identical to that of the underlying hardware  Benefits Simpler VMM Lower performance degradation of guest execution  Drawbacks Guest OS to be ported for the para-API Source modifications to replace sensitive instr’s/operations with ‘hypercalls’  Depth of Para-Virtualization Shallow: replace sensitive instructions Deep: replace sensitive subsystems (e.g., process model, page-table management, etc.)

23 23 Hardware Assisted Virtualization  Return to classic trap-and-emulate model in hardware  Add hardware enhancements to enable efficient full virtualization VMM gets an exclusive privilege level Allow configuration of traps into monitor Unmodified guest OS can run efficiently in VM  Examples Intel VT-X (“Vanderpool”) AMD-V (“Pacifica”) ARM VE (Virtualization Extensions) VM User VM Kernel VMM Level 0 Level 1 Level 2 System User

24 24 Overview  CPU Background  Virtualization and VMs  CPU Virtualization  Memory Virtualization Background Software Virtualization Shadow Page Tables Hardware-supported Memory Virtualization Nested Page Tables Ring Compression

25 25 Traditional Address Spaces 04GB Physical Address Space RAM ROMDevices Frame Buffer

26 26 Traditional Address Spaces 04GB Current Process 04GB Operating System Virtual Address Space Physical Address Space RAM ROMDevices Frame Buffer

27 27 Memory Management Unit (MMU)  Virtual Address to Physical Address Translation Works in fixed-sized pages Page Protection  Translation Look-aside Buffer TLB caches recently used Virtual to Physical mappings  Control registers Page Table location Current ASID Alignment checking

28 28 Traditional Address Translation w/Architected Page Tables Virtual Address Physical Address Process Page Table TLB Operating System’s Page Fault Handler

29 29 Virtualized Address Spaces 04GB Current Guest Process 04GB Guest OS Virtual Address Spaces Physical Address Spaces Virtual RAM Virtual ROM Virtual Devices Virtual Frame Buffer

30 30 Virtualized Address Spaces 04GB Current Guest Process 04GB Guest OS Virtual Address Spaces Physical Address Spaces Virtual RAM Virtual ROM Virtual Devices Virtual Frame Buffer 04GB Machine Address Space RAM ROM Devices Frame Buffer

31 31 Virtualized Address Spaces w/ Shadow Page Tables Virtual Address Space 04GB Physical Address Space 0 Machine Address Space 0 Guest Page Table VMM PhysMap 4GB Shadow Page Table VAPA Guest PAMA VMM VAMA Shadow Hardware PT Walker

32 32 Virtualized Address Translation w/ Shadow Page Tables Virtual Address Machine Address Emulated TLB Page Table Guest Page Table PMap TLB A

33 33 Issues with Shadow Page Tables  High cost of walking guest page tables in software  High cost of VMM entries and exits  Page Table Consistency Shadow needs to track guest page table deltas

34 34 Virtualized Address Spaces w/ Nested Page Tables Virtual Address Space 04GB Physical Address Space 0 Machine Address Space 0 Guest Page Table VMM PhysMap 4GB

35 35 Virtualized Address Translation w/ Nested Page Tables Virtual Address Machine Address Guest Page Table PhysMap By VMM 1 2 TLB 3 2 3

36 36 Issues with Nested Page Tables  Positives Simplifies monitor design No need for the monitor to maintain coherence  Negatives Guest page table is in physical address space Need to walk PhysMap multiple times  Other Memory Virtualization Hardware Assists Monitor Mode has its own address space

37 37 Interposition with Memory Virtualization: Page Sharing VM1 Virtual Physical Machine Read-Only Copy-on-write VM2 Virtual Physical

38 38 Ring Compression  VMM must share guest’s Virtual Address space Exception / Interrupt handlers Binary Translation Cache Emulation routines  Need to protect: VMM from guest Guest kernel from guest user  Multiplex available memory protection mechanisms Guest User Guest Kernel VMM Level 0 Level 1 Level 2 System User

39 39 Copyright ® VMware, Inc. All Rights Reserved. Thank You!

40 40 Hybrid Approach  Binary Translation for the Kernel  Direct Execution (Trap-and-emulate) for the User  U.S. Patent 6,397,242 DirectExec OK? Direct Execution Jump to Guest PC Yes Execute In TC TC Validate Handle Priv. Instruction No Callout Trap

41 41 Types of MMUs  Architected Page Tables x86, x86-64, ARM, IBM System/370, PowerPC Hardware defines page table layout Hardware walks page table on TLB miss  Architected TLBs MIPS, SPARC, Alpha Hardware defines the interface to TLB Software reloads TLB on misses Page table layout free to software  Segmentation / No MMU Low-end ARMs, micro-controllers Para-virtualization required

42 42 Issues with Emulated TLBs  Guest page table consistency Rely on Guest’s need to invalidate TLB Guest TLB invalidations caught by monitor, emulated  Performance Guest context switches flush entire software TLB

43 43 Shadow Page Tables Guest Page Table Shadow Page Table Guest Page Table Guest Page Table Shadow Page Table Shadow Page Table Virtual CR3 Real CR3

44 44 Guest Write to CR3 Guest Page Table Shadow Page Table Guest Page Table Guest Page Table Shadow Page Table Shadow Page Table Virtual CR3 Real CR3

45 45 Guest Write to CR3 Guest Page Table Shadow Page Table Guest Page Table Guest Page Table Shadow Page Table Shadow Page Table Virtual CR3 Real CR3

46 46 Undiscovered Guest Page Table Virtual CR3 Guest Page Table Shadow Page Table Guest Page Table Guest Page Table Shadow Page Table Shadow Page Table Real CR3 Guest Page Table

47 47 Undiscovered Guest Page Table Guest Page Table Shadow Page Table Guest Page Table Guest Page Table Shadow Page Table Shadow Page Table Virtual CR3 Real CR3 Guest Page Table Shadow Page Table

48 48 Memory Tracing  Call a monitor handler on access to a traced page Before guest reads After guest writes Before guest writes  Modules can install traces and register for callbacks Binary Translator for cache consistency Shadow Page Tables for cache consistency Devices Memory-mapped I/O, Frame buffer ROM COW

49 49 Memory Tracing (cont.)  Traces installed on Physical Pages Need to know if data on page has changed regardless of what virtual address it was written through  Use Page Protection to cause traps on traced pages Downgrade protection Write traced pages downgrade to read-only Read traced pages downgrade to invalid

50 50 Trace Callout Path Virtual Address Machine Address Emulated TLB Page Table Guest Page Table PMap TLB 6 7 Mapping installed with downgraded privileges

51 51 Hiding the Monitor – Options for Trap-and-Emulate  Address space switch on Exceptions / Interrupts Must be supported by the hardware  Occupy some space in guest virtual address space Need to protect monitor from guest accesses Use page protection Need to emulate guest accesses to monitor ranges Manually translate guest virtual to machine Emulate instruction Must be able to handle all memory accessing instructions

52 52 Hiding the Monitor – Options for Binary Translation  Translation cache intermingles guest and monitor memory accesses Need to distinguish these accesses Monitor accesses have full privileges Guest accesses have lesser privileges  On x86 can use segmentation Monitor lives in high memory Guest segments truncated to allow no access to monitor Binary translator uses guest segments for guest accesses and monitor segments for monitor accesses


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