Presentation is loading. Please wait.

Presentation is loading. Please wait.

Chapter 8: Memory Management

Similar presentations

Presentation on theme: "Chapter 8: Memory Management"— Presentation transcript:

1 Chapter 8: Memory Management
Background Swapping Contiguous Allocation Paging Segmentation Segmentation with Paging

2 Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at three different stages. Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes. Load time: Must generate relocatable code if memory location is not known at compile time. Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers).

3 Multistep Processing of a User Program

4 Logical vs. Physical Address Space
The concept of a logical address space that is bound to a separate physical address space is central to proper memory management. Logical address – generated by the CPU; also referred to as virtual address. Physical address – address seen by the memory unit. Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme.

5 Memory-Management Unit (MMU)
Hardware device that maps virtual to physical address. In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. The user program deals with logical addresses; it never sees the real physical addresses.

6 Dynamic relocation using a relocation register

7 Dynamic Loading A routine is not loaded until it is called. All routines are kept on disk in a relocatable load format. Better memory-space utilization; unused routine is never loaded. Useful when large amounts of code are needed to handle infrequently occurring cases such as error routines. No special support from the operating system is required. It is the responsibility of the users to design their programs to take advantage of this method. OS may help programmer by providing library routines to implement dynamic loading.

8 Dynamic Linking Dynamic linking : Linking postponed until execution time. With dynamic linking, a small piece of code, called stub, which indicates how to locate the appropriate memory-resident library routine or how to load the library if the routine is not already present. Stub replaces itself with the address of the routine, and executes the routine. Thus, next time that particular code segment is reached, the library routine is executed directly, incurring no cost for dynamic linking. Operating system needs to check if the routine is in process’s memory address. Dynamic linking is particularly useful for libraries. A library may be replaced by a newer version and all programs that reference the library will reference the new version. Without dynamic linking, all such programs would need to be relinked.

9 Swapping A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images. Roll out, roll in – swapping variant used for priority-based scheduling algorithms; lower-priority process is swapped out so higher-priority process can be loaded and executed. Major part of swap time is transfer time; total transfer time is directly proportional to the amount of memory swapped. Modified versions of swapping are found on many systems, i.e., UNIX, Linux, and Windows.

10 Schematic View of Swapping

11 Contiguous Memory Allocation
Main memory is usually split into two partitions: Resident operating system, usually held in low memory with interrupt vector. User processes then held in high memory. Single-partition allocation Relocation-register scheme used to protect user processes from each other, and from changing operating-system code and data. Relocation register contains value of smallest physical address; limit register contains range of logical addresses – each logical address must be less than the limit register.

12 Hardware Support for Relocation and Limit Registers

13 Contiguous Allocation (Cont.)
Multiple-partition allocation Hole – block of available memory; holes of various size are scattered throughout memory. Adjacent holes are merged to form larger holes When a process arrives, it is allocated memory from a hole large enough to accommodate it. Operating system maintains information about: a) allocated partitions b) free partitions (holes) OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 10 process 2 process 2 process 2 process 2

14 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes. First-fit: Allocate the first hole that is big enough. Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size. Produces the smallest leftover hole. Worst-fit: Allocate the largest hole; must also search entire list. Produces the largest leftover hole. First-fit and best-fit better than worst-fit in terms of speed and storage utilization.

15 Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous. Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference makes memory internal to a partition not being used. This occurs if the OS maintains holes of fixed sizes. Reduce external fragmentation by compaction Shuffle memory contents to place all free memory together in one large block. Compaction is possible only if relocation is dynamic, and is done at execution time. I/O problem Latch job in memory while it is involved in I/O. Do I/O only into OS buffers.

16 Paging Paging is another approach for solving the external fragmentation problem Physical address space of a process can be noncontiguous. Divide physical memory into fixed-sized blocks called frames. Divide logical memory into blocks of same size called pages. Page size (like the frame size) is determined by the hardware. The size of a page is typically between 512 bytes and 16MB, depending on the computer architecture. (Under Linux, you can use getpagesize() system call to get the size of a page) OS needs to Keep track of all free frames. To run a program of size n pages, OS needs to find n free frames and load program. Set up a page table to translate logical to physical addresses. No external fragmentation occurs when paged memory allocation is used because any free frame can be allocated to a process. However, Internal fragmentation can occur.

17 Address Translation Scheme
Address generated by CPU is divided into: Page number (p) – used as an index into a page table which contains base address of each page in physical memory. Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit.

18 Address Translation Architecture

19 Paging Example

20 Paging Example

21 Free Frames Before allocation After allocation

22 Implementation of Page Table
Page table is generally kept in main memory, even though hardware implementation of page table is possible. Page-table base register (PTBR) points to the page table. Page-table length register (PRLR) indicates size of the page table. In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) Each entry in the TLB consists of two parts: a key and a value. When the TLB is presented with an item, the item is compared with all keys simultaneously. If the item is found, the corresponding value field is returned. Typically the number of entries in the TLB is small (between 64 and 1,024) because the hardware is expensive.

23 TLB (continuetd) If the page number searched is not in the TLB (called TLB miss), a memory reference to the page table must be made. When the frame number is obtained, it is used to access memory and the page number and the corresponding frame number are added to the TLB so that they will be found quickly on the next reference. If the TLB is full, the OS must select one to replace using some algorithm such as LRU, random, or MRU, etc. Moreover, some TLBs allow the entries to be wired down, meaning that they cannot be removed from the TLB. Typically TLB entries for kernel code are wired down. Some TLBs also store address-space identifiers (ASIDs) in each TLB entry. An ASID uniquely identifies each process and is used for address space protection for that process. This also allows TLB contain entries for several different processes simultaneously.

24 Paging Hardware With TLB

25 Effective Access Time Associative Lookup (i.e., TLB access time) =  microseconds Assume memory cycle time is x microseconds Hit ratio – percentage of times that a page number is found in the associative registers; hit ratio is related to number of associative registers. Hit ratio =  Effective Access Time (EAT) EAT = (x + )  + (2x + )(1 – ) = x(2 - ) + 

26 Memory Protection Memory protection is implemented by associating protection bit with each frame (pages can be read-only, read-write, execute-only). Normally these bits are kept in the page table. Also one more bit valid-invalid bit is attached to each entry in the page table: “valid” indicates that the associated page is in the process’ logical address space, and is thus a legal page. “invalid” indicates that the page is not in the process’ logical address space.

27 Valid (v) or Invalid (i) Bit In A Page Table

28 Page Table Structure Hierarchical Paging Hashed Page Tables
Inverted Page Tables

29 Hierarchical Page Tables
If page table cannot fit in one page or memory cannot be allocated contiguously to hold the page table, then (i) break up the logical address space into multiple page tables or (ii) use multi-level paging For example, under two-level paging, the page table itself is paged.

30 Two-Level Paging Example
A logical address (on 32-bit machine with 4K page size) is divided into: a page number consisting of 20 bits. a page offset consisting of 12 bits. Since the page table is paged, the page number is further divided into: a 10-bit page number. a 10-bit page offset. Thus, a logical address is divided as follows: where p1 is an index into the outer page table, and p2 is the displacement within the page of the page table. page number page offset p1 p2 d 10 10 12

31 Two-Level Page-Table Scheme

32 Address-Translation Scheme
Address-translation scheme for a two-level 32-bit paging architecture

33 Hashed Page Tables Commonly used in address spaces > 32 bits.
The virtual page number is hashed . Each entry in the hash table consists of three fields: (1) the virtual page number, (2) the value of the mapped frame, and (3) a pointer to the next element in the linked list. This page table contains a chain of elements hashing to the same location. For locating the frame number of a page, the page number is hashed into the hash table. Page numbers are compared in the chain of entries in the corresponding location in the hash table, searching for a match. When a match is found, the corresponding physical frame is extracted.

34 Hashed Page Table

35 Inverted Page Table Only One Page Table is maintained for all the processes. One entry for each real frame of memory. Entry consists of the virtual address of the page stored in that frame with information about the process that owns that page. Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. Use hash table to limit the search to one — or at most a few — page-table entries.

36 Inverted Page Table Architecture

37 Shared Pages Shared code
One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes. Private code and data Each process keeps a separate copy of the code and data. The pages for the private code and data can appear anywhere in the logical address space.

38 Shared Pages Example

39 Segmentation Memory-management scheme that supports user’s view of memory. A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

40 User’s View of a Program

41 Logical View of Segmentation
1 4 2 3 1 2 3 4 user space physical memory space

42 Segmentation Architecture
Logical address consists of a two tuple: <segment-number, offset>, Segment table – maps two-dimensional physical addresses; each table entry has: base – contains the starting physical address where the segments reside in memory. limit – specifies the length of the segment. Segment-table base register (STBR) points to the segment table’s location in memory. Segment-table length register (STLR) indicates number of segments used by a program; segment number s is legal if s < STLR.

43 Segmentation Architecture (Cont.)
Relocation. dynamic by segment table Sharing. shared segments same segment number Allocation. first fit/best fit external fragmentation

44 Segmentation Architecture (Cont.)
Protection. With each entry in segment table, associate validation bit = 0  illegal segment read/write/execute privileges Protection bits associated with segments; code sharing occurs at segment level. Since segments vary in length, memory allocation is a dynamic storage-allocation problem. A segmentation example is shown in the following diagram

45 Segmentation Hardware

46 Example of Segmentation

47 Sharing of Segments

48 What is used in real systems
Sun SPARC architecture (with 32 bit addressing) uses three level paging scheme Motorola 68030(32 bit addressing) supports four-level paging scheme UltraSPARC (64 bit addressing) and PowerPC use inverted page tables Segmentation with paging is used in Intel Pentium Segment- ation unit Paging unit Physical Memory Linear address Logical address Physical address CPU

Download ppt "Chapter 8: Memory Management"

Similar presentations

Ads by Google