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KAIST 전산학과 맹 승 렬 Memory Management Unit.

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Presentation on theme: "KAIST 전산학과 맹 승 렬 Memory Management Unit."— Presentation transcript:

1 KAIST 전산학과 맹 승 렬 Memory Management Unit

2 년 전문대교수연수 2004 CS310 Microprocessors & Lab The Memory System  Embedded systems and applications The memory system requirements: vary considerably –Simple blocks –Multiple types of memory –Caches –Write buffers –Virtual memory

3 년 전문대교수연수 2004 CS310 Microprocessors & Lab Memory management units  Memory management unit (MMU) translates addresses:  Protection checks CPU main memory management unit logical address physical address

4 년 전문대교수연수 2004 CS310 Microprocessors & Lab Memory management tasks  Allows programs to move in physical memory during execution  Allows virtual memory: memory images kept in secondary storage; images returned to main memory on demand during execution  Page fault: request for location not resident in memory

5 년 전문대교수연수 2004 CS310 Microprocessors & Lab Address translation  Requires some sort of register/table to allow arbitrary mappings of logical to physical addresses  Two basic schemes: segmented paged  Segmentation and paging can be combined (x86)

6 년 전문대교수연수 2004 CS310 Microprocessors & Lab Segments and pages memory segment 1 segment 2 page 1 page 2

7 년 전문대교수연수 2004 CS310 Microprocessors & Lab Segment address translation segment base addresslogical address range check physical address + range error segment lower bound segment upper bound

8 년 전문대교수연수 2004 CS310 Microprocessors & Lab Page address translation pageoffset pageoffset page i base concatenate

9 년 전문대교수연수 2004 CS310 Microprocessors & Lab Page table organizations flat page descriptor tree page descriptor

10 년 전문대교수연수 2004 CS310 Microprocessors & Lab Caching address translations  Large translation tables require main memory access  TLB: cache for address translation Typically small

11 KAIST 전산학과 맹 승 렬 ARM Memory Management Unit

12 년 전문대교수연수 2004 CS310 Microprocessors & Lab ARM Memory Management  System control coprocessor(CP15) Memory Write Buffers Caches  Registers Up to 16 primary registers Physical registers in CP15 more than 16  Register access instructions MCR (ARM to CP15) MRC (CP15 to ARM)

13 년 전문대교수연수 2004 CS310 Microprocessors & Lab Cached MMU memory system

14 년 전문대교수연수 2004 CS310 Microprocessors & Lab ARM Memory Management  MMU can be enabled and disabled  Memory region types: section: 1 Mbytes block large page: 64 Kbytes small page: 4 Kbytes tiny Page: 1 Kbytes  Two-level translation scheme (why?) First-level table Second-level table Page table size for 4-KB pages : 2 20 X 4 bytes = 4 MB

15 년 전문대교수연수 2004 CS310 Microprocessors & Lab ARM address translation offset1st index2nd index physical address Translation table base register 1st level table descriptor 2nd level table descriptor concatenate

16 년 전문대교수연수 2004 CS310 Microprocessors & Lab First-level descriptors  AP: access permission  C,B: cachability and bufferability

17 년 전문대교수연수 2004 CS310 Microprocessors & Lab Section descriptor and translating section references CP reg 2: 16 KB boundary 4K Entries 1 MB block (section) Max: 16KB

18 년 전문대교수연수 2004 CS310 Microprocessors & Lab Coarse Page table descriptor 4 K entries Max: 16KB 256 entries Max: 1KB

19 년 전문대교수연수 2004 CS310 Microprocessors & Lab Fine page table descriptor 1 K entries Max: 4 KB

20 년 전문대교수연수 2004 CS310 Microprocessors & Lab Second-level descriptor

21 년 전문대교수연수 2004 CS310 Microprocessors & Lab Translating large page references

22 년 전문대교수연수 2004 CS310 Microprocessors & Lab Access permissions  System (S) and ROM (R) in CP15 register 1

23 년 전문대교수연수 2004 CS310 Microprocessors & Lab TLB functions  Invalidate instruction TLB  Invalidate instruction single entry  Invalidate entire data TLB  Invalidate data single entry  TLB lockdown

24 KAIST 전산학과 맹 승 렬 MPC 850 MMU

25 년 전문대교수연수 2004 CS310 Microprocessors & Lab MPC850 MMU  Does not support some PowerPC MMU features  4-, 16-, 512- Kbyte, or 8-Mbyte pages 1-KB subpages for 4-Kbyte pages  Separate instruction and data MMUs Can be disabled separately  Supports up to 16 virtual address spaces  Supports 16 access protection groups

26 년 전문대교수연수 2004 CS310 Microprocessors & Lab MPC 850 MMU, cont’d  Separate 8-entry, fully-associative data translation lookaside buffer (DTLB) and instruction TLB (ITLB)  High performance and low power consumption  TLB locking, invalidation

27 년 전문대교수연수 2004 CS310 Microprocessors & Lab Address Translation  Translation disabled MSR[DR], MSR[IR] Effective address = physical address  Translation enabled TLB –SW handles the table lookup and TLB reload with little HW assistance in the MPC 850 MMU supports a multiple virtual address space –Address space ID (ASID)

28 년 전문대교수연수 2004 CS310 Microprocessors & Lab Address Translation, cont’d Not implemented in the DTLB

29 년 전문대교수연수 2004 CS310 Microprocessors & Lab TLB operation Current Address ID Privilege level 8?

30 년 전문대교수연수 2004 CS310 Microprocessors & Lab Translation Table (4 KB pages)

31 년 전문대교수연수 2004 CS310 Microprocessors & Lab Translation Tables (1 KB pages)

32 년 전문대교수연수 2004 CS310 Microprocessors & Lab Level-One descriptor

33 년 전문대교수연수 2004 CS310 Microprocessors & Lab Level-Two Descriptor 1KB protection 4KB page HW assist 4KB page 1KB subpage

34 년 전문대교수연수 2004 CS310 Microprocessors & Lab Page Size

35 년 전문대교수연수 2004 CS310 Microprocessors & Lab Programming Model

36 년 전문대교수연수 2004 CS310 Microprocessors & Lab Programming Model (cont’d)

37 년 전문대교수연수 2004 CS310 Microprocessors & Lab TLB operations  tlbia: translation lookaside buffer invalidate all  tlbie: translation lookaside buffer invalidate entry  Locking TLB entries

38 년 전문대교수연수 2004 CS310 Microprocessors & Lab Locking TLB Entries IMMU control register (MI_CTR bit 4) DMMU control register (MD_CTR bit 4)

39 년 전문대교수연수 2004 CS310 Microprocessors & Lab DTLB reload


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