Presentation on theme: "Copper Damascene Plating Process Development Engineer"— Presentation transcript:
1 Copper Damascene Plating Process Development Engineer 1/5/06Brandon BrooksProcess Development EngineerSemitool Confidential
2 Outline Why Cu Interconnects? Damascene Process Flow Parameters Affecting Cu InterconnectsBackside Clean and Bevel Etch
3 Damascene Plating?The damascene in Cu damascene plating refers to the inlay of gold or some other metal into a substrate.
4 Al Cu Interconnect Metal Properties Best! Resistivity Resistivity Why Cu Interconnects?Interconnect Metal PropertiesAlCuWMelting Pt (°C)6601,0833,410Oxidation in AirRapid; Self-SealingSlow; Not Self-SealingInertResistivity (mW-cm)Crystalline2.821.775.6As Deposited*8-11Self-Diffusion Coefficient 100 °C2.1·10-202.1·10-30Coefficient of Thermal Expansion (Unit/°C)24·10-617·10-64.3·10-6* Alloy (Si, Cu)Best! Resistivity Melting PointThermal ExpansionElectromigrationCu Resistivity Melting PointThermal ExpansionElectromigrationAlAl was the metal of choice for chip interconnects up until the late 90s. There are still many chipmakers that are using Al for their interconnect metal, but as feature sizes shrink, more fabs are making the switch to Cu.Cu offers several benefits over Al. Al is very prone to electromigration. Electromigration is the movement of metal atoms with e- flow. Over time electromigration will lead to breaks in the line causing shorts in the metal interconnect. Also Al has a high resistivity, which leads to decreased performance from RC delay in the circuit.Because of these characteristics, Cu was the natural choice to replace Al. Cu has a low Rs and strong resistance to electromigration, as well as a higher melting point and decreased thermal expansion when compared to Al. These characteristics make Cu a higher performance and more reliable choice for interconnect metal.
5 Interconnect Metal Properties Why Cu Interconnects?Interconnect Metal PropertiesAlCuAgEtch PropertiesCl & Br PlasmasF & Cl PlasmasEtch Rate (Å/min)5,000500Cu has a very slow etch rateCu halides are solid at normal temperaturesChanging from Al to Cu interconnects requires new process flowEnter Damascene platingWhen chipmakers were using Al interconnects, they could use a subtractive metal etch process to form the Al interconnects. However, the halide plasma that was used to etch Al interconnects couldn’t be used on Cu because Cu halides are solid at room temperature. Thus a new process flow for metal interconnects had to be approached. This new approach became known as Damascene plating. It was called damascene because instead of forming the interconnect lines from the subtractive etch of the metal, the metal interconnect was inlayed into features that were formed by the subtractive etch of dielectric instead.
6 Typical Damascene Process Flow Dielectric DepositionPhotoresist DepositionUV ExposureDevelop PhotoresistEtch DielectricRemove PhotoresistBarrier DepositionSeed Layer DepositionElectrochemical Deposition (ECD)Backside Clean and Bevel EtchAnnealChemical Mechanical Polish (CMP)Repeat Steps 1-10 for Every Metal LayerToday’s Main TopicsThis is a simplified process flow for the formation of Cu damascene interconnects. I have a movie that will show this process flow, but I will focus on steps 7-12 for the majority of the presentation.
7 Damascene Process Flow Negative Resist: Usually Dry-Film and UV Exposure HardensPositive Resist: Usually Liquid Spin On and UV Exposure Softens
8 Key Factors Affecting Cu Interconnect Performance Copper Interconnect ParametersKey Factors Affecting Cu Interconnect PerformanceGap-FillCD UniformityOverburdenAnnealThere are 4 key factors that determine Cu interconnect performance:Gap-fill refers to how well we fill the trench with Cu. Our goal is to completely fill the trench without voiding.Uniformity and Overburden are parameters that affect the subsequent process in the damascene interconnect flow, which is CMP. And finally, Anneal refers to the thermal recrystalliztion of the the Cu film, which leads to increased Cu grain size.AMD’s 9 Cu Levels
9 Key Parameters for Gap-Fill Copper Interconnect Parameters: Gap-FillKey Parameters for Gap-FillSeed and Barrier LayersUniformityThicknessPlating RecipeHot Start (Initiation)Fill Current DensityWaveformPlating ChemistryInorganicOrganic0.12m, 8.3:1AR TrenchesThe first parameter that affects gap-fill is the seed and barrier layer uniformity and thickness. These parameters are very important and our part of the previous process in the flow. Without good seed and barrier layers, then we cannot deposit a good Cu film.The second parameter affecting gap-fill is the plating recipe. There are 3 main portions to the recipe: Hot start, which refers to the initial entry of the wafer into our plating chemistry. Fill current density, which refers to the amount of current passed through the wafer during gap-fill. And Waveform, which refers to the power setting of the current used to plate the Cu on the wafer.The third paramter affecting gap-fill is plating chemistry, which has both inorganic and organic components.ECD Seed plus Nanoplate ECD Cu
10 Physical Vapor Deposition (PVD) Effects Copper Interconnect Parameters: Gap-FillSeed and Barrier LayersPhysical Vapor Deposition (PVD) EffectsThe seed and barrier layers are deposited using a PVD process. The PVD chamber’s main features are a target made of the metal to be deposited and a chuck that holds the wafer directly under the target. In the PVD process, high energy Ar ions bombard the target, which is made of the metal to be deposited. This ion bombardment causes metal ions to fall off of the target and fall to the wafer surface.The barrier is deposited first. The function of the barrier is twofold, to provide a barrier to the diffusion of Cu into the dielectric and to provide adhesion between the dielectric and metal interconnect.The seed is deposited second. Its function is to provide an electrical contact for the ECD process.This PVD process is a line of sight process, which leads to some issues. It is very difficult to get good sidewall coverage in the trench. Usually the bottom of the trench and the top of the trench are covered well, but the sides of the trench are harder to cover. If you have too thick of a barrier or seed, then this will lead to an increased overhang, which will cause pinch off during the ECD process.You also need to have as uniform as possible coverage of the sidewall, if there is poor sidewall coverage, then it will lead to sidewall voiding in the ECD process.
11 Edge Shadowing Optimized Seed Layer Seed and Barrier Layer Uniformity Copper Interconnect Parameters: Gap-FillSeed and Barrier Layer UniformityThe left SEM image shows sidewall voiding due to excessive edge shadowing, while the right image has no voiding because of the good sidewall coverage.Edge ShadowingOptimized Seed Layer
12 1500Å Total Seed Thickness 2000Å Total Seed Thickness Copper Interconnect Parameters: Gap-FillSeed and Barrier Layer Thickness1500Å Total Seed Thickness2000Å Total Seed Thickness0.30micron, 4.8:1 AR ViasThe left image in this slide shows an optimized seed layer, while the right image shows seam voiding due to pinch off in the ECD step caused by too much overhang from the PVD step.
13 2X Fill Rate on the 2V Hot Start Copper Interconnect Parameters: Gap-FillPlating Recipe Hot Start2X Fill Rate on the 2V Hot StartNo Hot Start2V Hot Start0.180 m Line Width Trenches48 Coulombs ECD
14 The Effect of Current Density upon Gap Fill Copper Interconnect Parameters: Gap-FillPlating Recipe Current DensityCurrent too LowCurrent too HighThe Effect of Current Density upon Gap FillBadGood0.35μm, 4.3:1 AR Vias0.18μm, 5.1:1 AR TrenchGap FillCurrent DensityLowHighOptimum Fillfor feature DOptimum CurrentWhen the current density is too low, then the organic portion of the bath doesn’t function properly and we get insufficient gap-fill. When the current density becomes too high, then we become mass transport limited on Cu and we get insufficient gap-fill.
15 DC plating provides better additive adsorption Copper Interconnect Parameters: Gap-FillPlating Recipe WaveformWaveformCu DiffusionAdditive AdsorptionBottom Up FillDirect Current (DC)-+Pulse DCPulse Reverse (PR)DC plating provides better additive adsorptionPulsed plating provides better Cu diffusion
16 Inorganic Components Organic Components Copper Sulfate (CuSO4) Copper Interconnect Parameters: Gap-FillPlating ChemistryInorganic ComponentsCopper Sulfate (CuSO4)Hydrochloric Acid (HCl)Sulfuric Acid (H2SO4)Organic ComponentsSuppressor (PEG)Accelerator (SPS)Leveler (Amine)Suppressor is generally a polyethlyene glycol compound. Accelerator is generally a sulfopropyl-disulfide compound. Leveler is an amine containing polymer
17 Copper Effect on Gap Fill Copper Interconnect Parameters: Gap-FillInorganic Plating ChemistryCopper Effect on Gap FillHigh CopperLow CopperFrom Linlin’s high cu bath work. Top Picture is Nanoplate POR bottom is high Cu bath. Dependency of gap fill on Cu is for a specific plating conditions. The lower the current density or with PR plating the weaker the correlation. We have seen similar results looking at diluted baths compared to the POR
18 Chloride Effect on Gap-Fill Copper Interconnect Parameters: Gap-FillInorganic Plating ChemistryChloride Effect on Gap-FillA minimum concentration( around 35-40ppm) of Chloride ions is required to gain maximum suppression (optimum gap fill). Beyond this there is not much effect on gap fill unless the concentration is very high. However, those conditions are not well defined.
19 Acid Effect on Gap Fill Inorganic Plating Chemistry pH 3 pH 2 pH 2 Copper Interconnect Parameters: Gap-FillInorganic Plating ChemistrypH 3pH 2Acid Effect on Gap FillpH 2Acid gives throwing power (conductivity). The more acid in the bath, the higher the current will be for a given potential. Also, the greater the amount of acid in the bath, the better the organic molecules will work.
20 Organic Effect on Gap Fill Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryOrganic Effect on Gap FillAcceleratorCatalytic effectRequires very small amount of Cl-Increased current for a given potentialSuppressorSuppresses depositionRequires Cl- to adsorb onto copper surfaceDecreases current for a given potentialLevelerSuppresses deposition at high current density areasVery low concentration (diffusion limited)
21 Cyclic Voltammetric Stripping Analysis (CVS) Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryCyclic Voltammetric Stripping Analysis (CVS)Stripping RegionACBA = VMSB = VMS + SuppressorC = VMS + Sup. & Accel.IPlating RegionIn CVS analysis, we sweep the voltage from positive to negative potential on a platinum rotating disk electrode in electrolyte. This voltage sweeping subsequently plates and strips a small amount of Cu from the electrolyte onto the platinum RDE. We then graph the current as a function of potential of the RDE and integrate the area under the stripping curve to calculate how much Cu was plated.V
22 Organic Plating Chemistry Copper Interconnect Parameters: Gap-FillOrganic Plating Chemistry0.10.20.30.010.020.030.040.05SuppressorConcentration80 g/lLow Acid (10g/l)High Acid 150 g/l510152025301234Accelerator80 g/l H2SO4WorseBetterStripping AreaThis is important because many of the additives in the bath are more effective with higher acid concentrations. This CVS plot show that with higher acid, the suppressor in Enthone’s Viaform chemistry are more effective passivators and the Accelerators more effective at increasing plating rates. This results in improved superfill characteristics.For a given Suppressor or Accelerator concentration, the higher the acid concentration, the better they work to perform gap-fill.
23 Organic Plating Chemistry Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryBlue = Suppressor bonded to a ClRed = AdditiveGreen = Leveler
24 Organic Plating Chemistry Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryInitial deposition is conformal. Notice that the leveler molecule has started to electrostatically adhere to the top corner of the trench due to the higher effective current density at these areas.
25 Organic Plating Chemistry Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryAs bottom corners close in accelerator begins to concentrate in the bottom of the feature due to the reduction in the surface area inside of the trench.
26 Organic Plating Chemistry Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryThe increased concentration of accelerator in the bottom of the feature facilitates bottom up gap-fill.
27 Organic Plating Chemistry Copper Interconnect Parameters: Gap-FillOrganic Plating ChemistryNote: the concentration of additive on the top of the filled feature. This leads to over bumping.
29 Key Parameters for Current Density Uniformity Copper Interconnect Parameters: CD UniformityKey Parameters for Current Density UniformityChemistryHigh AcidLow AcidCFD ReactorElectric Field ControlUniformity in this case refers to both uniformity of current density and uniformity of the ECD Cu depositIntel: 8 Cu Levels
30 Generalized Electrochemical Schematic Copper Interconnect Parameters: CD UniformityGeneralized Electrochemical SchematicElectrolytic Copper DepositionAmmeterV0+Current Density = CurrentSurf. AreaCurrent Pathe-e-ElectrolyteCu2+Cu2+This is a simplified soluble anode schematic.SurfaceAreaCu0 Cu2++2e-Cu2++2e- Cu0Anode(Oxidation)Cathode(Reduction)
31 Rcat Relec V Ranode= 0 Rcat 1/Seed Thickness Rcat Wafer Radius Copper Interconnect Parameters: CD UniformityRelec 1/Bath ConductivityRcat 1/Seed ThicknessRcat Wafer RadiusRelecRanode= 0V+ElectrolyteCathode(Thin)Anode(Thick)Rcat= Surface Area= AreaV=IRIf you take a section of wafer with the same surface area at the center and edge of the wafer, then the amount of current passing through the wafer at the edge and center are given by the following equations.
32 How To Make Small? V Rcat Relec Rcat Current Density Throughput Copper Interconnect Parameters: CD UniformityHow To MakeSmall?RelecRanode= 0V+ElectrolyteCathode (Thin)Anode (Thick)RcatEdgeI LoopCenterVCurrent DensityThroughputRcatSeed Layer ThicknessWafer RadiusRelecBath ConductivityIf you decrease voltage, then you mess with a critical gap-fill parameter, current density, as well as throughput capability. You can decrease your cathode resistance by increasing your seed layer thickness or decreasing your wafer diameter, both of which are the exact opposite of what happens when the technology node shrinks. The only thing left is to increase your electrolyte resistivity by decreasing the bath conductivity, which minimizes, but does not fix the problem.
33 Conductivity at Various Bath Conditions Copper Interconnect Parameters: CD UniformityConductivity at Various Bath Conditions100200300400500600Conductivity (mS/cm)175 g/l H2SO417 g/l Cu80 g/l H2SO450 g/l Cu10 g/l H2SO4“Low” Acid“High” Acid70247511At higher acid concentrations, Cu is less soluble. So if we decrease the bath conductivity we have tampered with 2 critical parameters for gap-fill. Cu concentration and acid concentration. So if we run an ECD process in a conventional single anode system, then we will not be able to run the best chemistries.
34 Terminal Effect Current Density Wafer Radius Plating Time Copper Interconnect Parameters: CD UniformityTerminal Effect0sec5sec15sec30sec60sec120secCurrent DensityWafer RadiusPlating Time(0,0)This difference in current from the center to the edge of the wafer is refered to as the terminal effect. The terminal effect cause a huge difference in the current density from the center to the edge of the wafers. As you can see, this difference dissipates over time as the Cu film thickness increases. By the end of plating, the CD is essentially equal from center to edge.
35 The Effect of Current Density upon Gap Fill Copper Interconnect Parameters: CD UniformityCurrent too LowCurrent too HighThe Effect of Current Density upon Gap FillBadGood0.35mm, 4.3:1 AR Vias0.18mm, 5.1:1 AR TrenchGap FillCurrent DensityLowHighOptimum Fillfor feature DOptimum CurrentAs you will remember from before, Current density is a critical parameter for gap-fill as well.
36 receiving the same process? Copper Interconnect Parameters: CD UniformityAre the center and edgereceiving the same process?This terminal effect then leads to differences in the type of process that a trench in the center of the wafer and a trench on the edge of the wafers is subject to. So, in a conventional reactor, we can have poor gap fill in the center and good on the edge or vice versa, due to this varying current density from the center to the edge.
37 V1 V2 Advanced Reactor Design: Multiple Anodes Copper Interconnect Parameters: CD UniformityAdvanced Reactor Design: Multiple AnodesRobust system that can handle multiple chemistriesBuilt for the future with the ability to handle shrinking die sizeCost effective ability to handle increasing wafer diametersV1 and V2 adjusted untilIndependent of Rc and RelecCathodeAnode2V1+V21Enter the multi-anode CFD reactor. By having multiple anodes, we effectively negate differences in current density from the center to the edge of the wafer by changing the potential of the anodes to give a uniform current density from the center to the edge of the wafer. The difference in current becomes independent of the chemistry and seed layer thickness that we use.
40 Superposition of Electric Field Copper Interconnect Parameters: CD UniformitySuperposition of Electric Field-120-100-80-60-40-2020406080100120Wafer Diameter (mm)Normalized Voltage at Cathode (V)Anode 1Anode 2Anode 3Anode 4Summed Field
41 133% <5% 20% <5% SEMITOOL - CFD Conventional High Acid Low Acid Copper Interconnect Parameters: CD Uniformity100 nm Seed layer, 1m depositionConventionalSEMITOOL - CFD141822263034Current Density (mA/cm^2)0sec5sec15sec30sec60sec120sec133%<5%High Acid511mS/cm141822263034255075100125150Current Density (mA/cm^2)0sec120sec20%255075100125150<5%Low Acid70mS/cmWafer Radius (mm)
42 Dynamic Compensation for Constant Current Density Copper Interconnect Parameters: CD UniformityDynamic Compensation for Constant Current Density1.01.52.02.520406080100120Deposition Time (sec)Anode Current (Amps)Anode 2Anode 3Anode 1Anode 4Current density is a function of time and wafer radius. Semitool’s 4-anode reactor allows us to dynamically change the currents to provide a uniform current density from the beginning to end of ECD.
43 Key Parameters for Overburden Copper Interconnect Parameters: OverburdenKey Parameters for OverburdenLocal Overburden (Overplating) – Fill StepChemistry3-Component2-ComponentWaveformDirect CurrentPulse ReverseGlobal Overburden – Cap StepHigh AcidLow AcidCFD ReactorThere are 2 types of Overburden: Local and Global. Local overburden refers to the step height of Cu between an area of sparsely occupied or even blanket features and an area of very dense features. Global overburden refers to the amount of copper that is plated after complete gap-fill and is taken off during CMP. Combinations of these 4 factors lead to differing amounts of local overburden.
44 3-Component Organic Package Pulse Reverse POR Step Up No Step Up Copper Interconnect Parameters: Local OverburdenDirect Current POR3-Component Organic PackageModerate Acid ElectrolytePulse Reverse POR2-Component Organic PackageHigh Acid ElectrolyteStep UpNo Step UpPulse Reverse Waveform leads to less overburden during the fill step. In order to achieve the same results with DC, higher concentrations of Leveler need to be used.
45 Planar Deposition Overplating Copper Interconnect Parameters: Local OverburdenInsufficient LevelerPlanar DepositionOptimized Organic ConditionsOverplatingPost-CMP Residual CuNo Post-CMP Residual CuPulse Reverse Waveform leads to less overburden during the fill step. In order to achieve the same results with DC, higher concentrations of Leveler need to be used.
46 Thickness Variation (Å) Copper Interconnect Parameters: Global Overburden-100mm100-800-600-400-200200400600800ÅRadial control ofThickness Variation (Å)Cu Thickness (Å)The multiple anode design of the CFD reactor lends itself to applyingWafer Diameter (mm)
47 Raider CFD Profile Before & After 30s CMP Copper Interconnect Parameters: Global OverburdenRaider CFD Profile Before & After 30s CMP16,00012,000CFD Profile before CMPThickness (A)8,000Uniform Post-CMP ProfileProfile after 30s CMP4,000POR Profile Before & After 30s CMP16,000The Semitool CFD reactor allows users to profile the global overburden to compensate for CMP nonuniformity.12,000POR Profile before CMPThickness (A)EarlyClearing!8,000Profile after 30s CMP4,000EdgeResidual!Wafer Diameter
48 Copper Interconnect Parameters: Global Overburden CMP Profile Matching
49 Key Parameters for Anneal Copper Interconnect Parameters: AnnealKey Parameters for AnnealTemperatureFeature SizeBarrier LayerThe least resistive Cu film is composed of the larger grained Cu. Grain orientation also, plays a role, but the Cu film that has the smallest grains will undoubtedly have the higher resistance. The higher the resistance, then the slower electrons will travel through the interconnect and the slower your device will be. Thus, we anneal after ECD to grow the Cu crystals.
50 Effect of Temperature Small Grains Large Grains As Deposited Copper Interconnect Parameters: AnnealEffect of TemperatureAs DepositedSelf AnnealedThermally AnnealedSmall GrainsLarge GrainsHigh temperature is necessary to completely anneal Cu inside of device features.
51 Effect of Feature Size Self-Anneal Furnace Anneal 1.0m Trenches Copper Interconnect Parameters: AnnealEffect of Feature Size1.0mTrenches0.25mTrenchesAs feature size increases, grain growth is easier.Self-AnnealFurnace Anneal
54 Why Backside Clean and Bevel Etch? Cu is a highly mobile ionBackside contamination can have adverse effects across the fabUnstable films on the edge of the wafer can cause surface damage at CMPObjectiveRemove bulk Cu on the edge of the waferDelaminationFlakingYield ProblemsRemove atomic Cu on the back of the waferCommon PhotolithographyCommon MetrologyCu ion diffusion
55 Capsule 1 Chamber Cut Away Backside Clean and Bevel EtchCapsule 1 Chamber Cut AwayEdge Exclusion HardwareCapsule 1 FeaturesHardware control of bevel etch (BE)0-4mm BE edge exclusion (EE) rangeNo front side protection neededBE & backside clean simultaneouslyClean N2 purged microenvironmentHardware sets capable of 1 to 3 mm bevel etch
56 Capsule Dynamics Front Side Inlet: Wafer Device Up Back Side Inlet: Backside Clean and Bevel EtchCapsule DynamicsWaferDevice UpSealChamber RotationBack Side Inlet:-Dilute Piranha SolutionDI H2ON2Front Side Inlet:
57 Capsule Dynamics Front Side Inlet: Wafer Device Up Back Side Inlet: Backside Clean and Bevel EtchCapsule DynamicsSealChamber RotationBack Side Inlet:-Dilute Piranha SolutionDI H2ON2Front Side Inlet:WaferDevice Up
58 Precision Control of Chemical Wrap-Around Backside Clean and Bevel EtchPrecision Control of Chemical Wrap-AroundA concentric 1.5mm EE BE clears the notchCritical Bevel Etch ParametersConcentricityComplete Cu ClearingClearing the Notch
59 Precision Control of Concentricity Backside Clean and Bevel EtchPrecision Control of ConcentricityConcentricity Spec (a) ≤ 0.2mm
60 Precision Control of Copper Removal Backside Clean and Bevel EtchPrecision Control of Copper RemovalE Beam Spot Magn WD 10 µm10.0kV x STI. Bevel EtchNo Copper on Edge Exclusion ZoneNo undercutTarget ECD 1.0µm1 µm ECD Copper1.5 mm Edge ExclusionProfilometer Reading52º Tilt on SEM<10 µm
61 Summary Why Cu Interconnects? Damascene Process Flow ResistivityReliabilityDamascene Process FlowPhotolithography to CMPParameters Affecting Cu InterconnectsGap-FillCurrent Density UniformityOverburdenAnnealBackside Clean and Bevel EtchBulk Cu on the EdgeAtomic Cu on the Backside
62 Acknowledgements John Klocke – Cu Damascene Group Leader Kevin Witt – Cu Damascene Business Development LeaderTom Ritzdorf – Director of ECD TechnologyJake Cook – Marketing CommunicationsAll Semitool personnel that have contributed data to this presentationMany of you probably have seen some of your own work in this presentation, so if you did, I thank you for your contributions. Thanks.