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PWM Pulse Width Modulation Ellen Qiulei Huang Juan Orphee Austin Farmer ME 4447/6405 November 6th, 2012.

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Presentation on theme: "PWM Pulse Width Modulation Ellen Qiulei Huang Juan Orphee Austin Farmer ME 4447/6405 November 6th, 2012."— Presentation transcript:

1 PWM Pulse Width Modulation Ellen Qiulei Huang Juan Orphee Austin Farmer ME 4447/6405 November 6th, 2012

2 Outline Introduction -- What is PWM? Analog vs. Digital Actuation Consideration on PWM frequency Implementation on the HCS12 --Register Setup Examples of PWM configuration using assembly and C -- Applications of PWM 2

3 Presenter: Ellen Qiulei Huang Introduction -- What is PWM? Analog vs. Digital Actuation Consideration on PWM frequency Implementation on the HCS12 -- Register Setup Examples of PWM configuration using assembly and C -- Applications of PWM 3

4 What is PWM? Pulse Width Modulation (PWM) is a technique for delivering partial power to a load via digital means. The on-off behavior changes the average power of signal. Output signal alternates between on and off within specified period. xEU xEU Ellen Qiulei Huang 4

5 Duty Cycle A percentage measurement of how long the signal stays on. Period (T) Duty Cycle (D) VLVL VHVH OnOff Ellen Qiulei Huang 5

6 Duty Cycle Duty Cycle: Average signal : (Usually, V L is taken as zero volts for simplicity.) Period (T) Duty Cycle (D) VLVL VHVH OnOff Ellen Qiulei Huang 6

7 Duty Cycle Characteristic The average value of a PWM signal increases linearly with the duty cycle Ellen Qiulei Huang 7

8 Types of PWM – Left Aligned Lead edge is fixed, the trailing edge is modulated. Period Duty Cycle ~60% V lo V hi OnOff Period V lo V hi OnOff Duty Cycle ~30% Ellen Qiulei Huang 8

9 Types of PWM – Right Aligned Trailing edge is fixed, lead edge is modulated. Period Duty Cycle ~60% V lo V hi On Off Period V lo V hi OnOff Duty Cycle ~30% Ellen Qiulei Huang 9

10 Types of PWM – Center Aligned Center of signal is fixed, both edges are modulated Period V lo V hi Period V lo V hi Duty Cycle ~30% Duty Cycle ~60% OnOff OnOff Ellen Qiulei Huang 10

11 Analog Generation of PWM Analog PWM signals can be made by combining a saw- tooth waveform and a sinusoid PWM output is formed by the intersection of the saw-tooth wave and sinusoid. PWM toggles when sine equals saw-tooth. Ellen Qiulei Huang 11

12 Digital Generation - Delta Method Limit signals are offset from a reference When output signal reaches limits, PWM state changes Ellen Qiulei Huang 12

13 Digital Generation - Delta Method Quantizer converts the difference between output and limits. Quantizer can be realized with a comparator whose output is 1 or 0 if the input signal is positive or negative. Ellen Qiulei Huang 13

14 Digital Generation - Delta Sigma Method PWM signal generated by Delta method Error = Ref – PWM Error is integrated. When integration signal reaches limit, PWM state changes. Ellen Qiulei Huang 14

15 Digital Generation - Delta Sigma Method Ellen Qiulei Huang 15

16 Choosing your PWM frequency Output signal (actuator response) Input signal (PWM) Ripple Ellen Qiulei Huang 16

17 17 Choosing your PWM frequency Resolution: Inversely proportional to the number of distinct duty cycles you can generate for a given period Transitions can only occur on a clock tick Frequency limited by your clock and desired resolution Example: 8 MHz clock, choose PWM to be 4 MHz Limited resolution: only 3 duty cycles to choose from Ellen Qiulei Huang

18 1.Must be at least 10 times higher than the control system frequency 2.Higher than 20kHz – audible frequency of sounds to avoid annoying sound disturbances. 3.If too low the motor is pulsed, not continuous, because the motor’s inductance can not maintain the current 4.Inverse of frequency should be much less than the motor/load time constant 5.Higher error from ripple voltages Consideration on PWM frequency Upper Limits Lower Limits 1.If too high the inductance of the motor causes the current drawn to be unstable 2.MOSFET transistor generates heat during switching 3.Limited by resolution of controller 4.Eddy currents generated in electromagnetic coils which lead to adverse heating 5.Heat losses in electromagnetic materials is proportional to frequency squared Ellen Qiulei Huang 18 Avoid ripple, Resolution loss, Power loss, Human hearing

19 Average value proportional to duty cycle, D Low power used in transistors used to switch the signal Fast switching possible due to MOSFETS and power transistors at speeds in excess of 100 kHz Digital signal is resistant to noise Less heat dissipated versus using resistors for intermediate voltage values Advantages of PWM 19 Ellen Qiulei Huang

20 Cost Complexity of circuit Voltage spikes Susceptible to Electromagnetic Interference Disadvantages of PWM 20 Ellen Qiulei Huang

21 Presenter: Juan Orphee 21 Introduction -- What is PWM? Analog vs. Digital Actuation Consideration on PWM frequency Implementation on the HCS12 --Register Setup Examples of PWM configuration using assembly and C -- Applications of PWM

22 Pulse Width Modulator: PWM8B6CV1 Use Port P Six 8-bit channels or three 16-bit channels for greater resolution Each channel produces an independent PWM signal Two choices of clock sources per channel which provides for a wide range of frequencies Juan Orphee

23 PWM Block Diagram -Each channel needs setup of the following registrars: 1)Enable/disable 2)Signal Polarity 3)Clock A or SA, B or SB 4)Prescale A and B clocks 5)Center Alignment Enable 6)Control Register 7)Prescale SA and SB clocks 8)Counter 9)Period 10)Duty Cycle 11)Emergency Shutdown Define PWM signal Juan Orphee Period Duty Cycle V lo V hi

24 PWM Register Memory Map Juan Orphee

25 PWME in address: $00E0 Set PWMEx to 1 to enable the channel Set PWMEx to 0 to disable the channel 1-PWM Enable Register (PWME) Juan Orphee

26 PWMPOL in address: $00E1 Set PPOLx to 0, signal goes from low to high Set PPOLx to 1, signal goes from high to low 2-PWM Polarity Register (PWMPOL) Zero Line Signal Starts Here Juan Orphee

27 PWMCLK in address: $00E2 Set PCLK(5/4/1)  0 to use clock A Set PCLK(5/4/1)  1 to use clock SA Set PCLK(3/2)  0 to use clock B Set PCLK(3/2)  1 to use clock SB Note: choice of Prescale will determine clock selection 3-PWM Clock Select Register (PWMCLK) Juan Orphee

28 4-PWM Prescale Clock Select Register (PWMPRCLK) Located at $00E3 Used to prescale clocks A and B -Similar for Clock B -If calculated prescaler > 128 then use clock SA -How to convert time (e.g. in seconds) to cycles? Time (sec) x Clock Frequency = Time (sec) x (Buss Clock/Prescaler) Juan Orphee N = bit resolution Desired PWD Frequency Bus Clock HCS12 = 8 MHz

29 Computing a Prescaler 29 Duty Cycle Period Time per clock cycle (sec) = Prescaler x Time (sec) per bus clock cycle T (sec) -Resolution = Maximum Clock Counts -Example: An 8 bit counter can count 2^N-1 = 255 clock cycles 125x10(-9) sec for HCS12

30 Located at $00E4 Set CAEx to 0 for left align signal Set CAEx to 1 for center align signal Note: – Can only be set when channel is disabled 5-PWM Center Align Enable Register(PWMCAE) Juan Orphee

31 Left vs. Center Aligned PWM Signal Starts Juan Orphee Not To Scale

32 PWMCTL : Located at $00E5 Set CONxy to 0 to keep 6 PWM channels separate (8-bit) Set CONxy to 1 to concatenate PWM channels x and y together (16-bit). x becomes the high byte and y becomes the low byte Channel y determines the configuration Bits PSWAI and PFRZ set either wait or freeze mode Note – Changes only occur when both channels are disabled 6-PWM Control Register (PWMCTL) Juan Orphee

33 7-PWM Scale A Register (SA Clock) (PWMSCLA) Located at $00E8 Programmable scaling of clock A to generate clock SA Note Juan Orphee

34 PWM Scale B Register (PWMSCLB) Located at $00E9 Programmable scaling of clock B to generate clock SB Note Juan Orphee

35 Located at $00EC through $00F1 One per channel It tracks the cycle counts When channel is enabled up-count starts Note – Writing to counter while a channel is enable can cause irregular PWM cycles 8-PWM Channel Counter Register (PWMCNT) Juan Orphee

36 Counter: Left vs. Center Aligned In the left aligned mode, the PWM counts up until (period-1) and resets to zero. In the center aligned mode, the PWM counts up until (period-1) and counts down to zero. Note: Period (PWMPER) is expressed in number of cycles PWM Signal Starts Juan Orphee

37 Located at $00F2 through $00F7 PWMPERx Store a hexadecimal value to limit maximum value of counter Note : Changes occur when one of following happen – Current period ends – Counter is written to – Channel is disabled 9-PWM Channel Period Register (PWMPER) Juan Orphee =$00F2 What is my PWMPER? PWMPER (cycles) = PWM Period(sec) x Clock Freq(cycles/sec)

38 Located at $00F8 through $00FD Store a hexadecimal value to control when signal changes Changes occur when: – Current period ends – Counter written to – Channel is disabled e.g for 60% duty cycle: PWMDTY = 0.6xPWMPER (in cycles) 10-PWM Channel Duty Register (PWMDTY) Juan Orphee

39 11-PWM Shutdown Register (PWMSDN) $00FE Juan Orphee

40 Presenter: Austin Farmer Introduction -- What is PWM? Analog vs. Digital Actuation Consideration on PWM frequency Implementation on the HCS12 - Register configuration Example of PWM configuration using Assembly and C Code Applications of PWM 40

41 PWM Configuration Example Use PWM Channel 0 Positive polarity (signal goes from high to low) Left aligned output Frequency: 40 kHz – Period = 1/Frequency = 1/40 kHz = 25 μs Choose clock source using resolution: – Bus clock frequency: 125 ns  25 μs / 125 ns = 200 cycles – 200 < 255, select clock A with prescaler = 1 Duty Cycle = 50% – (50% * 200 cycles) = 100 cycles Austin Farmer 41

42 Configuration Example: Assembly Code Austin Farmer PWMEEQU$00E0* 1-PWM Enable Register PWMPOLEQU$00E1* 2-PWM Polarity Register PWMCLKEQU$00E2* 3-PWM Clock Select Register PWMPRCLKEQU$00E3* 4-PWM Prescale Clk Select Reg. PWMCAEEQU$00E4* 5-PWM Center Align Enable Reg. PWMPER0EQU$00F2* 9-PWM Channel 0 Period Register PWMDTY0EQU$00F8* 10-PWM Channel 0 Duty Register ORG$1000 LDAA#$01 STAAPWMPOL*Positive polarity (starts high) LDAA#$00 STAAPWMCAE*Left aligned output STAAPWMCLK*Use Clock A STAAPWMPRCLK *Clock A prescaler = 1 LDAA#$C8 STAAPWMPER0*Period =(25μs/125ns)= 200 = $C8 LDAA#$64 STAAPWMDTY0*Duty cycle=(200*50%)= 100 = $64 LDAA#$01 STAAPWME*Enable PWM Channel 0...

43 Configuration Example: C Code #include /* common defines and macros */ #include /* derivative information */ #pragma LINK_INFO DERIVATIVE “mc9s12c32” // Set up chip in expanded mode MISC = 0x03; PEAR = 0x0C; MODE = 0xE2; //Set up PWM Registrer PWMCLK = 0;// Sets source clock to clock A PWMPOL = 1;// Positive Polarity (signal goes from high to low) PWMCTL = 0;// Makes all channels 8-bit PWMCAE = 0;// Signals are left aligned PWMPER0 = 200;// Sets the period of the signal to 200 clock cycles PWMDTY0 = 100;// Makes the duty cycle 100 clock cycles (50% of 200) PWMPRCLK = 0;// Sets the prescaler to 1 PMWE = 1;// Enables and starts Channel 0 of PWM …. Austin Farmer 43

44 Motivation for PWM In the past, motors were controlled at intermediate speeds by using variable resistors to lower delivered power (inefficient) –Example: Foot pedal on sewing machines is a variable resistor connected in series to control speed PWM provides a more compact way of applying adjustable power to devices Austin Farmer 44

45 Applications of PWM Voltage regulation DC Motors Telecommunications Audio and Video Effects Austin Farmer 45

46 Application: Voltage Regulation PWM is used in efficient voltage regulators With appropriate duty cycle, the output will approximate voltage at the desired level Switching noise can be filtered Austin Farmer 46

47 Application: DC Motors Commonly used to control the speed of a DC motor Continuous application of PWM cycle results in average voltage being applied to motor Output speed of motor is proportional to input voltage EU EU Used in Lab 3 Austin Farmer 47

48 Application: Telecommunications Pulses of various lengths will be sent at regular intervals (the carrier frequency of the modulation) The widths of the pulses correspond to specific data values encoded at one end and decoded at the other Leading edge of the data used as clock because small offset is included More resistant to noise effects than binary data alone Austin Farmer 48

49 Applications: Audio and Video In audio circuits, PWM can produce an effect similar to a chorus Used in new class of efficient audio amplifiers PWM dimming provides superior color quality in LED video display (millions of colors) Austin Farmer 49

50 Questions?


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