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* Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 1 de 24 * Pepe PICmicro 

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Presentation on theme: "* Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 1 de 24 * Pepe PICmicro "— Presentation transcript:

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2 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 1 de 24 * Pepe PICmicro 

3 © 2002 Microchip Technology Incorporated. All Rights Reserved. * Pepe Sagitrón Jornadas MMIV / 1-ARCHI / 2 Display Drivers D / A A / D FLASH USART SPI I 2 C CAP COMP PWM EEPROM Power Drivers

4 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 3 Harvard architecture with 2 level Pipeline –RISC single cycle MHz (1 MIPS) MHz (5 MIPS) Mhz (8.3 MIPS) 100 4x10 Mhz (10 MIPS) –High speed application with low power consumption Very short Instrution Sets (33 / 35 / 58 / 76) –Single word* and Orthogonal –Easy / Fast learning curve Powerful instructions (12 / 14 / 16 / 16 bit width) –Highest code efficiency Wide peripherals range –Timers, CCP, SSP, SCI, PSP, A/D, D/A, EEPROM... Smooth Upward / Downward migration Comprendiendo los PICs: Prestaciones RISC

5 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 4 Broad suite of powerful and low cost PC based tools –PICSTART Plus –PROMATE & Socket modules –ICEPIC with interchangeable emulator probes –MPLAB-ICE 2000 with interchangeable emulator probes –MPLAB-ICD2 In-Circuit Debugger Integrated software tools –MPASM, MPLIB, MPLINK –MPLAB-SIM –MPLABC-18, CCS, HITECH, IARC –FuzzyTECH (Windows) –MPLAB (Windows Integrated Development Environment) Over 200 Third Party Products Comprendiendo los PICs: Facilidad de Desarrollo

6 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / week lead-time over 90% of portfolio Windowed, FLASH, OTP, QTP, SQTP, and ROM –8, 18, 28, 40 and 64 JW and plastic DIP –8, 18 and 28 SOIC, 20 and 28 SSOP –44, 68 and 84 PLCC and PQFP Very comprehensive technical support literature –Microcontroller Data Book –Embedded Control Handbook –CDROM Technical Library Thousands of happy customers in most applications areas Internet web site : Strong Distributor Network Comprendiendo los PICs: Servicio al Cliente

7 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 6 Traditional Von-Neumann architecture fetches instruction and data from the same memory area. Limits operating bandwidth. C P U 8 = 8 Program & Data Memory Program & Data Memory Harvard architecture uses two separate memory spaces for instruction and data. Different program and data bus widths are possible. Access is concurrent. Increases throughput. Data Memory Data Memory C P U 8 Program Memory Program Memory 12/ 14/ 16 ¿ Qué es la arquitectura Harvard ?

8 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 7 Long Word Instruction Separate instruction/data busses allow different bus-widths Base-Line PIC16C5X instruction word length is optimized to 12 bits. Mid-Range PIC16CXX instruction word length is optimized to 14 bits. High-End PIC17C4X instruction word length is optimized to 16 bits. Harvard Architecture enables single-word/single-cycle instructions Example:MOVEimmediate, Acc PIC16C5X:MOVLW#imm 1 word / 1machine cycle CISC XX: #imm 2 bytes / 2 fetch cycles + exec nK words on-chip memory of PIC´s is roughly equivalent to 2 x nK Bytes of other 8-bit microcontrolers. Single cycle access increases execution bandwidth 1100 imm op code imm MOVE Eficacia del Código de los PICs

9 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 8 The high performance of the PIC´s can be attributed to the following architectural features: Harvard architecture Instruction pipelining Register file concept Single-cycle instructions All instructions single-word Reduced instruction set Long Word Instruction Orthogonal instruction set Características de los PICmicro  MCU

10 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 9 Data Bus 8 R A M General Purpose Register R A M General Purpose Register Ports Timer 0 RTCC Timer 0 RTCC 12 Instruction Bus EPROM / FASH Program Memory x 12 EPROM / FASH Program Memory x 12 Diagrama de Bloques gama BASE Program Counter x Decode & Control 33x Decode & Control Instruction Reg. Execute Instruction Reg. Execute Instruction Reg. Fetch Instruction Reg. Fetch 2 Level Stack 9-11 Goto / Call 9/8 +2 File Select Addr Mux Direct Addr Status Work Reg A L U Data Mux Literals 8 D. Reset Timer Power on Reset Watchdog Timer Oscilator Driver D. Reset Timer Power on Reset Watchdog Timer Oscilator Driver

11 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 10 Status File Select 35x Decode & Control 35x Decode & Control Instruction Reg. Execute Instruction Reg. Execute Instruction Reg. Fetch Instruction Reg. Fetch R A M General Purpose Register R A M General Purpose Register Program Counter Work Reg A L U x Data Mux Addr Mux 8 Level Stack 13 Goto / Call 11/11 +2 Literals 8 Direct Addr 7 8 Data Bus 8 14 Instruction Bus Timer 0 RTCC Timer 0 RTCC Ports Interrupts 1 Power-up Timer Osc start Timer Power on Reset Watchdog Timer Oscilator Driver Power-up Timer Osc start Timer Power on Reset Watchdog Timer Oscilator Driver Special Hardware Peripherals Special Hardware Peripherals Diagrama de Bloques gama MEDIA 8-9 EPROM / FLASH Program Memory x 14 EPROM / FLASH Program Memory x 14

12 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 11 Status File Select 58x Decode & Control 58x Decode & Control Instruction Reg. Execute Instruction Reg. Execute Instruction Reg. Fetch Instruction Reg. Fetch R A M General Purpose Register R A M General Purpose Register Program Counter Work Reg A L U x Data Mux Addr Mux 16 Level Stack 16 Goto / Call Lcall 13/ Literals 8 Direct Addr Data Bus 8 16 Instruction Bus Timer 0 RTCC Timer 0 RTCC Ports Interrupts 4 Power-up Timer Osc start Timer Power on Reset Watchdog Timer Oscilator Driver Power-up Timer Osc start Timer Power on Reset Watchdog Timer Oscilator Driver Int./Ext. Program & Data Memory x 16 Int./Ext. Program & Data Memory x Special hardware Peripherals Special hardware Peripherals Diagrama de Bloques gama ALTA

13 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 12 Status 3x File Select ++ 76x Decode & Control 76x Decode & Control Instruction Reg. Execute Instruction Reg. Execute Instruction Reg. Fetch Instruction Reg. Fetch R A M General Purpose Register R A M General Purpose Register Program Counter Work Reg A L U x Data Mux Addr Mux 31 Level Stack 21 Goto / Call Branch / Rcall 21/21 11/11 Literals 8 Direct Addr 8+4 / 12&12 12 Data Bus 8 16 Instruction Bus Timer 0 RTCC Timer 0 RTCC Ports Interrupts 2 Power-up Timer Osc start Timer Power on Reset Watchdog Timer Oscilator Driver w PLL Power-up Timer Osc start Timer Power on Reset Watchdog Timer Oscilator Driver w PLL Int./Ext. Program & Data Memory x 8 + x 16 Int./Ext. Program & Data Memory x 8 + x Special Hardware Peripherals Special Hardware Peripherals Diagrama de Bloques gama MEJORADA

14 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / XXXXXXXX l Look-up Table Example movf DisplayValue,W callSevenSegmentDecode movwfPORTB gotoContinue SevenSegmentDecode addwfPCL,F retlwB’ ’ ;decode 0 retlwB’ ’ ;decode 1 retlwB’ ’ ;decode 2 retlwB’ ’ ;decode 3 retlwB’ ’ ;decode 4 retlwB’ ’ ;decode 5 retlwB’ ’ ;decode 6 retlwB’ ’ ;decode 7 retlwB’ ’ ;decode 8 retlwB’ ’ ;decode 9 b e g a f d c PIC16CXX RB0 RB1 RB2 RB3 RB4 RB5 RB6 a b c d e f g g a f d c W Register I/O Port B movf DisplayValue,W callSevenSegmentDecode addwfPCL,F retlwB’ ’ ;decode 5 movwfPORTB Descodificador de 7 segmentos

15 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 14 P1 MOVF REGX,W R1 ADDWF PCL,F P2 CALL R1 R2 RETLW 0xB7 P3 MOVWF PORTB R3 RETLW 0x5A P4... R4... Rn RETLW 0xFF In most microcontrollers, instructions are fetched and executed sequentially PIC´s pipelined architecture overlaps fetch and execution, making single-cycle instruction execution possible... Fetch P1 Exec P1 Fetch P2 Exec P2 Fetch P3 Exec NOP...Fetch R1 Exec R1 Fetch R2 Exec NOP...Fetch Rn Exec Rn Fetch Rm Exec NOP...Fetch P3 Exec P3... Any program branch (such GOTO, CALL,... or Write to PC) takes two cycles PICs Trabajo en Paralelo... AN 556

16 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 15 P1 MOVF REGX,W R1 ADDWF PCL,F P2 CALL R1 R2 RETLW 0xB7 P3 MOVWF PORTB R3 RETLW 0x5A P4... R4... Rn RETLW 0xFF Cycles Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Next PA P4 R2 R3 WR PC R1 R2 Rn AD Prg. P3 R1 R2 RD Inst. P3 R1 R2 Next Ins. P2 NOP R1 RD Data X - - X Exec X X X WR Data X - - X...PICs Trabajo en Paralelo

17 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 16 General Purpose Registers (RAM) Other SFRs PORTA FSR STATUS PCL TMR0 INDF W Register ALU DataMemory l RAM is a bank of general purpose general purpose registers. registers. l Peripherals (I/O) are registers. registers. l All instructions operate on any register. operate on any register. l Long word instruction allows direct allows direct addressing of registers. addressing of registers. Los registros

18 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 17 Several Interrupt Sources Interrupts have one vector, Priority set by Software Global and individual Interrupt Enables The return address is pushed into stack When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt Several interrupts wake processor up from sleep Hardware interrupt latency machine cycles PIC16FXXX Interrupciones

19 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / Interrupt Sources 4 Hardware Prioritized Interrupt Vectors Peripheral Interrupts have 1 vector, priority set by Software. Global and individual Interrupt Enables The return address is pushed into stack When an interrupt is responded to, the GLINTD bit is automatically set to disable any further interrupt Several interrupts wake processor up from sleep Hardware interrupt latency machine cycles PIC17C4X/75X/76X Interrupciones

20 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 19 Multiple Interrupt Sources 2 Hardware Prioritized Interrupt Vectors Interrupts priority set by Software. Global and individual Interrupt Enables The return address is pushed into stack The context (WREG, STATUS and BSR) could be saved on the shadow registers When an interrupt is responded to, the GIE bit ( GIEH or GIEL) is automatically cleared Several interrupts wake processor up from sleep Hardware interrupt latency machine cycles PIC18FXXXX Interrupciones

21 * Pepe © 2002 Microchip Technology Incorporated. All Rights Reserved. Sagitrón Jornadas MMIV / 1-ARCHI / 20 l 12 MHz l 1 to 4 cycle instructions l Cycle = clk / 12 = 1  s ; byte/cycle Int_Srv:; 0/3 to 9 PUSHPSW; 2/2 PUSHACC; 2/2 MOV PSW,#08h; 3/2 Interrupciones Comparativa con MCS-8X51... l 12 MHz l 1 to 2 cycle instructions l Cycle = clk / 4 =  s ; word/cycle Int_Srv: ; 0/3 MOVWF tempWRG ; 1/1 MOVF STATUS,W ; 1/1 BCF STATUS,RP0 ; 1/1 MOVWF tempSTA ; 1/1


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