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Hangzhou, April 2002Lou Scheffer1 Timing Closure Today Lou Scheffer Cadence San Jose, CA

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Presentation on theme: "Hangzhou, April 2002Lou Scheffer1 Timing Closure Today Lou Scheffer Cadence San Jose, CA"— Presentation transcript:

1 Hangzhou, April 2002Lou Scheffer1 Timing Closure Today Lou Scheffer Cadence San Jose, CA

2 Hangzhou, April 2002Lou Scheffer2 Timing Closure Today Timing more accurate as flow progresses Sometimes an earlier stage thinks timing is OK, but it fails a later stage Need to repeat one or more steps with tighter constraints We have a timing closure problem when this process fails. Symptoms include: Non-convergence Too many iterations Solution achievable, but this flow cannot find it. Design Entry Synthesis Timing Place Timing Route Timing

3 HangzhouLou SchefferII-3 The Timing Closure Problem

4 Hangzhou, April 2002Lou Scheffer4 Examples of Problems Design Worst slack / # misses Cycle time Tech SynthesisPlaced C1 -1 / / 38k 7.5 ns.25 µm V1 0 / / 15k 7.5 ns.18 µm T / / 164k ns.18 µm P / / 43k 8 ns.25 µm V / / ns.18 µm

5 HangzhouLou SchefferII-5 Agenda n Timing Analysis Overview n Traditional design flows n Summary of DSM Problems n Correction Methods Overview n Hierarchy and Timing Closure n Block Level Timing Closure n Experimental Results n Summary

6 HangzhouLou SchefferII-6 Timing Analysis n Give accurate time values on each pin/port of the network n Has to deal with design changes in optimization toolbox n Static Timing Analysis u Simulation far too slow in optimization environment u Accuracy is more than enough

7 HangzhouLou SchefferII-7 Timing Analysis Requirements n Choose combination of timing analyzer and delay calculator which are appropriate for level of design u give the best accuracy u for performance that can be tolerated n Timing Analysis / Delay calculation must be able to cope with logic design changes u Incremental u Highest performance possible u Non-linear delay models

8 HangzhouLou SchefferII-8 Timing Analysis Requirements n Must handle… u Difference between rising and falling delays u Delay dependent on slew rate u Slew and delay dependent on output load u Non-linear delay equations

9 HangzhouLou SchefferII-9 Late Mode Analysis Definitions Constraints: assertions at the boundaries Constraints: assertions at the boundaries –Arrival times: AT a, AT b –Required arrival time: RAT x Delay from a to x is the longest time it takes to propagate a signal from a to x Delay from a to x is the longest time it takes to propagate a signal from a to x Slack is required arrival time - arrival time. Slack is required arrival time - arrival time. a b x c y

10 HangzhouLou SchefferII-10 Example a b x c y 1 1

11 HangzhouLou SchefferII-11 Early mode analysis a b x c y Definitions change as follows Definitions change as follows –longest becomes shortest –slack = arrival – required Not as important since early violations are easier to fix Not as important since early violations are easier to fix 1 1

12 HangzhouLou SchefferII-12 Delay modeling a b x Propagation Arcs cl do Test Arc Timing Model

13 HangzhouLou SchefferII-13 Agenda n Timing Analysis Overview n Traditional design flows n Summary of DSM Problems n Timing Correction Overview n Approaches to Fixing Timing Closure n Experimental Results n Summary

14 HangzhouLou SchefferII-14 Traditional Design Flows Design Entry Synthesis Timing Place Timing Route Timing 1.Tech independent optimization 2.Tech mapping 3.Rudimentary timing correction

15 HangzhouLou SchefferII-15 Logic Synthesis n Technology independent optimization u General goal: reduce connections, literals, redundancies, area n Technology mapping u Map logic into technology library n Timing correction added next u Find and fix critical timing paths u Fix electrical violations (load, slew)

16 HangzhouLou SchefferII-16 Traditional Design Flows Design Entry Synthesis w/Timing Place w/Timing Route Timing Integrate timing with synthesis and placement 1.Tech independent optimization 2.Tech mapping 3.Timing correction

17 HangzhouLou SchefferII-17 Traditional Design Flows Design Entry Synthesis/Place ment w/Timing Global Route Detailed Route Timing Integrate timing with synthesis and placement 1.Tech independent optimization 2.Tech mapping 3.Placement 4.Timing Correction

18 HangzhouLou SchefferII-18 Traditional Design Flows Design Entry Synthesis and Placement w/Timing and Global route Detailed Route Timing Integrate timing with synthesis, placement and global route 1.Tech independent optimization 2.Tech mapping 3.Placement 4.Timing Correction 5.Global route

19 HangzhouLou SchefferII-19 Agenda n Timing Analysis Overview n Traditional design flows n Summary of DSM Problems n Correction Methods Overview n Hierarchy and Timing Closure n Block Level Timing Closure n Experimental Results n Summary

20 HangzhouLou SchefferII-20 The Wall n Logic designers concentrate on logic and timing (as understood by synthesis) n Design work done in abstract world u Was gates and wire load models u Now may include placement and global route n Throw design over the wall when complete n Physical designers concentrate on layout and ability to route n Effective method for many years

21 HangzhouLou SchefferII-21 General CMOS Problems n Low drive strengths / low power u Capacitance (not intrinsic delay) plays a large role in performance u Huge variability – range between slowest possible and fastest possible n Noise affects delay u IR drop a big percentage of supply u Crosstalk can change delay by a factor of 2

22 HangzhouLou SchefferII-22 Additional DSM Problems n High density / huge designs n Very thin and resistive wires n Very high frequencies u Inductance becomes more important n Smaller voltages u IR drop a bigger fraction of signal swing n Clock skew and latency n Electromigration and noise

23 HangzhouLou SchefferII-23 Clock Distribution Problems n Most common design approach requires close to zero skew n CMOS / DSM problems all affect clocks n Distribution problem increasing u Number of latches/flip-flops growing significantly n Power consumed in clock tree significant u  I and noise also of concern

24 HangzhouLou SchefferII-24 Process Designers are trying to help n Many metal layers n Different metal pitches u Small pitch for local interconnect u Big pitch/thick metal for long, fast wires n Copper wires, thick metal to lower R n SOI – Silicon On Insulator n Low k dielectrics n These help but are not enough

25 HangzhouLou SchefferII-25 Agenda n Timing Analysis Overview n Traditional design flows n Summary of DSM Problems n Correction Methods Overview n Hierarchy and Timing Closure n Block Level Timing Closure n Experimental Results n Summary

26 HangzhouLou SchefferII-26 Timing Correction n Fix electrical violations (slew and load). Takes priority since needed for reliability. u Resize cells u Buffer nets u Copy (clone) cells n Fix timing problems u Local transforms (bag of tricks) u Path-based transforms

27 HangzhouLou SchefferII-27 Local Transforms n Resize cells n Buffer or clone to reduce load on critical nets n Decompose large cells n Swap connections on commutative pins or among equivalent nets n Move critical signals forward n Pad early paths n Area recovery

28 HangzhouLou SchefferII-28 Transform Example Delay = 4 ….. Double Inverter Removal ….. Delay = 2

29 HangzhouLou SchefferII-29 Resizing b a d e f ? b a A b a C 0.026

30 HangzhouLou SchefferII-30 Cloning b a d e f g h 0.2 ? b a d e f g h A B Can also isolate critical sinks

31 HangzhouLou SchefferII-31 Buffering b a d e f g h 0.2 ? b a d e f g h B B

32 HangzhouLou SchefferII-32 Redesign Fan-in Tree a c d b e Arr(b)=3 Arr(c)=1 Arr(d)=0 Arr(a)=4 Arr(e)= c d e Arr(e)=5 1 1 b 1 a

33 HangzhouLou SchefferII-33 Redesign Fan-out Tree Longest Path = Longest Path = 4 Slowdown of buffer due to load

34 HangzhouLou SchefferII-34 Decomposition

35 HangzhouLou SchefferII-35 Swap Commutative Pins 2 c a b a c b Simple Sorting on arrival times and delay works

36 HangzhouLou SchefferII-36 Move Critical Signals Forward Based on ATPG Based on ATPG –linear in circuit size –Detects redundancies efficiently Efficiently find wires to be added and remove. Efficiently find wires to be added and remove. –Based on mandatory assignments. a b c d e a b e d c

37 HangzhouLou SchefferII-37 Path-based Transforms n Path-based resizing n Unmap / remap a path or cone n Slack stealing n Retiming

38 HangzhouLou SchefferII-38 Slack Stealing Take advantage of timing behavior of level sensitive registers (latches) Take advantage of timing behavior of level sensitive registers (latches) C1 C2 Slack = 0 C1 C2 Slack = +1 Slack = -1 C1 C2 01 2

39 HangzhouLou SchefferII-39 Retiming Delay=3 Delay=2 Forward Backward A more aggressive optimization since it changes the function

40 HangzhouLou SchefferII-40 Solutions to Timing Closure n Carry hierarchical logic design into physical n Hand / Custom design n Improved analysis n More sophisticated clock design n Modify existing flows n More physically knowledgeable tools u Many variations: combined synthesis/place/route, gain based synthesis, etc.

41 HangzhouLou SchefferII-41 Agenda n Analysis Methods Overview n Traditional design flows n Summary of DSM Problems n Correction Methods Overview n Hierarchy and Timing Closure n Block Level Timing Closure n Experimental Results n Summary

42 HangzhouLou SchefferII-42 Hierarchy and Physical Design n Logical hierarchy can be carried over into physical design n Seems natural top-down approach, using floorplanning as a firm guide to physical design n Use of hierarchy offers many advantages and many possible problems n A new generation of tools for this problem

43 HangzhouLou SchefferII-43 Pin Assignment and Timing Budgeting Each block requires: n Content definition u Partitioning n Pin locations n Clock/timing definition u Set_input_delay u Set_output_delay u Set_drive u Set_load u Path exceptions (false, multicycle paths) Block 1 Block 3 Block 2 L L L

44 HangzhouLou SchefferII-44 Hierarchy and Physical Design Advantages… n Run time of P&R tools n Blocks can be built independently n Early (and valuable) knowledge of global wires n Limited wire delay within macro may allows simpler methodologies n Contains the problem size n Extends naturally to SOC and mixed A/D chips n May be the only real method available

45 HangzhouLou SchefferII-45 Physical Hierarchy Disadvantages n Possible to overconstrain the design in many ways (see next slide) n Hierarchy usually logic-based, not physically-based u Designed for logical correctness, not physical implementation

46 HangzhouLou SchefferII-46 Physical Hierarchy Overconstraints n Placement solution perhaps overconstrained u Logical gates may not fit naturally in a rectangle n Ability to find a routable solution hindered u Can’t detour through neighboring cell n Boundary conditions explode and must be managed carefully to avoid surprises u A recent IBM design had 17,000 top level connections. A bad timing constraint on any one can make the whole design infeasible

47 HangzhouLou SchefferII-47 Hierarchy Example Plots

48 HangzhouLou SchefferII-48 Hierarchy Example Plots

49 HangzhouLou SchefferII-49 Hierarchy Example Plots

50 HangzhouLou SchefferII-50 The Challenges n How to derive sensible partitioning? n How to achieve die utilization similar to “flat” approach? n How to achieve clock speed and skews similar to “flat” approach? n How to automatically generate optimal pin assignments for each module? n How to automatically come up with realistic timing budgets for each module?

51 HangzhouLou SchefferII-51 GDSII Chip assembly routing Top level buffering, clock balancing, and power grid Physical synthesis / placement and routing Silicon Virtual Prototype hierarchical partitioning and placement RTL / gates Top LevelBlock Level Basic Approach to solution n Example tool – First Encounter n Start with a Silicon Virtual Prototype A near final quality ‘flat’ placement Near legal routing Known feasible solution for timing and routability Use this solution to guide the final implemention Partitioning, pin assignment, timing constraints Build the blocks with more detailed tools.

52 HangzhouLou SchefferII-52 Physical Data Accurate timing and routability data in hours instead of days or weeks const..lib netlist Physical Prototype Complete “flat” physical design (proves timing and routability) VERY FAST Full-Chip Physical Prototype a = b + c IP Logic Design: RTL, gates, IP, “black box” Hand off a floorplan OR full placement Placement Scan Opt.Trial Route RC Extract Delay CalcSTAClock Tree IPO Power Silicon Virtual Prototype Basic Approach continued Confidence the design will work once the blocks are re-assembled into the complete IC Block-Level Physical Synthesis and/or Route

53 HangzhouLou SchefferII-53 In-Context Hierarchical Partitioning n Pin assignment n Timing budgeting n Clock tree generation n Power grid planning Partitioning Independent block-level implementation SoC assembly

54 HangzhouLou SchefferII-54 In-Context Pin Assignment n Full-chip prototype results in optimal pin placement u Results in narrower channels and reduced die size u Reduces the routing congestion u Improves the chip timing Accurate Physical Prototype Flat Full-Chip Top Level Partition View

55 HangzhouLou SchefferII-55 In Context Timing Budgeting Each block requires: n Clock definition n Set_input_delay n Set_output_delay n Set_drive n Set_load n Path exceptions (false, multicycle paths) Block 1 Block 3 Block 2 L L L Accurate timing budgets result in predictable timing convergence

56 HangzhouLou SchefferII-56 Agenda n Analysis Methods Overview n Traditional design flows n Summary of DSM Problems n Correction Methods Overview n Hierarchy and Timing Closure n Block Level Timing Closure n Experimental Results n Summary

57 HangzhouLou SchefferII-57 Blocks have timing closure problems, too n Didn’t the big flat placement guarantee blocks are feasible? No, because u Block may not have been defined when global constraints were set u Global placer does not deal with all DSM effects u Block may be too hard for the relatively simple global placer (which must be very fast) u Requirements change as project progresses u Process technology may have changed u …..

58 HangzhouLou SchefferII-58 Hand/Custom Design n Mentioned for completeness u Hurts productivity u Yields highest performance n Can only fix a few things – for example: u Can realistically fix timing or crosstalk problems on a few nets u Cannot realistically change the size of blocks

59 HangzhouLou SchefferII-59 Improved Analysis Helps n Plot shows slack by net for two designs n A 10% timing delta -> many more bad nets u Often the difference between success and failure

60 HangzhouLou SchefferII-60 More accurate analysis n Crosstalk induced delay u Old approach – overestimate coupling C u Better – compute nominal timing + xtalk delta n Customer example from CadMos u Ignore crosstalk completely400 MHz F Not an acceptable alternative u Coupling Caps overestimated by 60%300 MHz u Nominal delays + computed crosstalk333 MHz u More accurate analysis gains 10% margin

61 HangzhouLou SchefferII-61 Increased accuracy helps n Global/detailed route correlation u Any global route better than Wire Load Models or Steiner trees, since global routes consider congestion u But to get that last 10%, need global/detailed router link F Knowing some nets must detour is good, but…. F Which net takes which detour is needed for good correlation

62 HangzhouLou SchefferII-62 Modified clock design n Zero skew is not necessary, and often not even desirable n We have the freedom to adjust clock arrival times at memory elements u This obtains more margin and thus helps convergence n Similar to retiming but less disruptive n Improvement very design dependent u If worst path is flip-flop to itself, doesn’t help n May impact scan chains

63 HangzhouLou SchefferII-63 Previous attempts to fix block closure n Without the radical step of combining synthesis and placement, designers have tried: u Allow placer to do sizing and buffering u Do post placement optimization F Simple transformations F Use existing placement u Do post placement re-synthesis F Complex transformations allowed F Needs incremental placement and extraction n But these have not been fully successful n Why? Re-examine the root cause of discrepancies u Wire load models and their limitations u Combined Synthesis/Placement/Routing

64 HangzhouLou SchefferII-64 Post-Placement Optimization Design Entry Synthesis w/Timing Place Route Timing Re-run Synthesis w/Timing 1.In-place optimizations 2.Minimally disturb placement optimizations

65 HangzhouLou SchefferII-65 Post-Placement Optimization n In-place (little or no placement impact) u Resizing (carefully) u Pin swapping, some tree rebuilding u Wire sizing / typing n Minimally disruptive u Resizing u Buffering u Cloning u Tree rebuilding u Cell removal

66 HangzhouLou SchefferII-66 In-place Optimization n Not too difficult n Can use extracted electrical data (C, RC) from placement tool u Some changes affect pin locations, but may be ignored u Tree rebuilding needs incremental extraction n Can use timing reports for timing data u But, accuracy suffers as changes are made u Real RC data replaced by estimates again

67 HangzhouLou SchefferII-67 In-place Optimization Placement & extraction Placed netlist C/RC data Optimization Opt’d netlist Resize swap pins rebuild trees

68 HangzhouLou SchefferII-68 Place-disruptive Optimization n Nets changing implies… u Must be able to recompute C and RC u May need to incrementally place new cells u Need incremental timing capability

69 HangzhouLou SchefferII-69 Place-disruptive Optimization Placement & extraction Placed netlist C/RC data Optimization with placer, timer, extractor Opt’d netlist Resize buffer clone cell removal rebuild trees

70 HangzhouLou SchefferII-70 What are the problems? n Getting the timing right u Different timers used at different stages u Do the optimizer and placer see the same worst paths as the static timer? n Design size / tool capacity u Using synthesis technology on flat designs

71 HangzhouLou SchefferII-71 More problems n Incompatible tools, formats u Placer, synthesizer, timer may all use different file format, may all be different vendors u Basic interoperability issues n Incremental placer needed for new cells u Doesn’t have to be smart u But might produce some infeasible solutions u Must be integrated with optimizer

72 HangzhouLou SchefferII-72 Still more challenges/problems n Extraction/Estimation of net data n Any optimization which significantly alters net topology needs this ability u Insert cells u Remove cells u Move connections from one cell to another n Steiner tree estimation n Net C and delay (RC) calculator n Do results match detail router and other extraction tools?

73 HangzhouLou SchefferII-73 Sample Optimization Results Design Worst slack / # misses Cycle time Tech SynthesizedPlacedOpt C1 -1 / / 38k -2 / ns.25 µm V1 0 / / 15k -0.3 / ns.18 µm T / / 164k -6 / 62k ns.18 µm P / / 43k -13 / 20k 8 ns.25 µm V / / / ns.18 µm

74 HangzhouLou SchefferII-74 Root Problem is Wire Load Models n Main problem: correlation between Pre- P&R estimates and Post-P&R extraction n If correlation is good… u Problems detected and potentially fixed early n If correlation is bad… u Problems detected late u Not a good situation! Need to re-write RTL is worst case for timing closure.

75 HangzhouLou SchefferII-75 Why are Wire Load Models Used? n Can’t complete layout until logic design is complete n Can’t complete logic design without timing n Can’t time without load and net delay data n Can’t extract load and net delay data until layout is complete n Can’t complete layout …

76 HangzhouLou SchefferII-76 WLM solution – use statistics n Don’t know specific layout data n But we know something about statistical properties n Average net load, average net delay n Further refine using other characteristics u Number of sinks u Size of design (number of circuits) u Physical size

77 HangzhouLou SchefferII-77 Correlation Pre/Post-P&R using averages n Wire load models give synthesis an estimate of physical design n We can correlate averages pre- and post- P&R as accurately as needed n If specific design has average behavior, its timing, on average, can be predicted n Otherwise, a pass through placement can provide correct WLM for a design, and get the averages right

78 HangzhouLou SchefferII-78 Timing and averages n WLMs OK for area, power (properties that are sums are well handled by statistics) n But, timing dictated by the worst specific path n That path is built of individual nets n One net can determine the speed of an entire design n Reality: poor correlation for relatively few nets can cause major headaches

79 HangzhouLou SchefferII-79 Correlation Pre/Post-P&R Averages and Wire Loads median mean Note the very long tails of this distribution

80 HangzhouLou SchefferII-80 Correlation Pre/Post-P&R C wire Data by Logic Design C wire Number of fan-outs

81 HangzhouLou SchefferII-81 Better Wire Load Models n How can we use information from one pass through physical design? n Adjust wire load model coefficients n Back annotate specific net load and delay data to the logic design n New problem: correlation of logic pre- and post- synthesis n But, there are fundamental limits to statistical models – a new approach is needed.

82 HangzhouLou SchefferII-82 A better (but harder) approach: Combine Synthesis, P & R n Don’t use wire load models at all n Synthesis does a trial placement as it runs u Loading found from estimated routes n For best results, must include global routing u Then, feed global route to detailed router u Or, do detailed route itself n Much better correlation and timing closure n No inter-tool data transfer headaches

83 HangzhouLou SchefferII-83 Example of Combined SP&R n 160k instances n 70 macros (blocks) n 5 layers, 0.18 micron n Target freq: 100Mhz Video Graphics Engine

84 HangzhouLou SchefferII-84 Conventional Flow n More than 20 Iterations n 89MHz best result w/manual changes Synthesis Static Timing syn2GCF SE Placement base optimization Detail route Floorplan DEF Extraction DRC Func. & Timing.TLF Physical LEF Global route Func. & Timing.lib Delay calc DC PT Pearl

85 HangzhouLou SchefferII-85 Combined SP&R Flow SE-PKS Floorplan DEF Extraction DRC Func. & Timing.TLF Physical LEF Delay calc EDIF netlist PKS Optimization Global Route Static Timing Pearl HE Static Timing PT TCL Constraints write_constraints Detail route n 100MHz final result, met timing n Correlation within % n One pass n 12hrs 20min runtime

86 HangzhouLou SchefferII-86 Slack Correlation Wire Load Based PKS Routed

87 HangzhouLou SchefferII-87 Enlargement of SP&R slack

88 HangzhouLou SchefferII-88 Results from combined SP&R Case size macros PKS timing max freq (MHz) instances (k) error (%) conventionalSP&R instances (k) error (%) conventionalSP&R % % % % % % % %

89 HangzhouLou SchefferII-89 Agenda n Traditional design flows n Summary of DSM Problems n Analysis Methods Overview n Correction Methods Overview n Approaches to Fixing Timing Closure n Experimental Results n Summary

90 HangzhouLou SchefferII-90 Experimental Results n For Hierarchical design, two objectives u Should be faster and higher capacity than a fully detailed flat design, to find problems earlier u Resulting partitions should be realizable n For Block Design, compare different strategies u Can overconstrain clock or wire models u Can do IPO or not after placing u Can allow placer to change size or not u Can test combined synthesis/placement against running the two tools separately

91 HangzhouLou SchefferII-91 Hierarchical Experimental results Design Import Detail Place Detail Route* RC Extract Delay Calculation Timing Analysis IPO Design Iteration 60x 4 min 4 hr 1x 3 hr 20 min 2 hr 50 min 56x 8 min 7 hr 30 min 57x 6 min 5 hr 45 min 33x 7 min 3 hr 50 min 7x 20 min 2 hr 15 min 5x 1 hr 50 min 9 hr 6x 5 hr 25 min 35 hr 40 min n Design 580K cells, 0.25um process, 5LM, 100MHz n Data collected on a 500MHz processor workstation n Resulting blocks were realizable (*) SPC Trial Route First Encounter Flow Traditional Flow

92 HangzhouLou SchefferII-92 How do different block design approaches compare? Jay McDougal of Agilent ran many flows on the same design 1. Overconstrain clock by various amounts 2. Accurate or conservative WLMs u Tried many levels of conservatism 3. Allow placer to size or not 4. Do post placement optimization or not 5. Physically knowledgeable synthesis

93 HangzhouLou SchefferII-93 Characteristics of sample design n Design not very difficult u ColdFire processor u 80K instances u 0.25 micron library u 5 layer process, not congestion dominated u Design goal was 180 MHz, known to be possible with this design u 85% of delay in gates; 15% in interconnect F 0.18/0.13 micron, bigger designs will show bigger differences between techniques

94 HangzhouLou SchefferII-94 Key to the plot of results n Basic flow – Design Compiler & QPlace n TDD = timing driven design u In addition to minimizing wire length and congestion, placer is given timing constraints and allowed to change gate sizes n IPO and PBO are post placement optimizers u IPO – runs on synthesis DB with back annotation u PBO – runs on physical DB with synthesis transforms n PKS = Physically Knowledgeable Synthesis (combined Synthesis/Place/Route)

95 HangzhouLou SchefferII-95 Comparison of Approaches Required Cycle time

96 HangzhouLou SchefferII-96 Comparison of Approaches Good area, but iterates between placement and synthesis, worst TTM, didn’t hit timing target One tool, no iteration, better TTM, hit timing target

97 HangzhouLou SchefferII-97 Agenda n Traditional design flows n Summary of DSM Problems n Analysis Methods Overview n Correction Methods Overview n Approaches to Fixing Timing Closure n Experimental Results n Summary

98 HangzhouLou SchefferII-98 Good News n At least we understand the problem u Analysis of timing is well understood u Transformations that help timing are well understood u DSM effects are painful but can be controlled

99 HangzhouLou SchefferII-99 Bad News n Cycle time and technology advances demand more and more sophisticated optimization techniques n In previous flows, corrections must be applied in separate tools n Disconnects among various tools involved increases turn-around-time and limits optimization

100 HangzhouLou SchefferII-100 Good News n The Bad News is commonly recognized n Many tool vendors, academics, in-house EDA researchers are working to solve these problems n A new generation of tools is already available that was designed from the ground up to address timing closure u Hierarchical and block design

101 HangzhouLou SchefferII-101 Bad News n These problems won’t be the last! n Each process generation brings new problems u Increased size u Weird process rules (antenna) u Possible new effects (single event upset)

102 HangzhouLou SchefferII-102 Summary n Timing closure is a very real problem n Large chips need hierarchical tools to help with partitioning and budgeting n Block tools must understand synthesis, placement and routing u wire load models have serious limitations n Best approach is combined synthesis/P&R n Experimental data backs this up

103 HangzhouLou SchefferII-103 Acknowledgements n Tony Drumm wrote the original set of slides for this lecture, including many of the examples. He credits: u Alex Suess u José Neves u Bill Joyner u IBM Rochester EDA folks n But the conclusions, and any mistakes, are mine

104 HangzhouLou SchefferII-104


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