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S. Veneziano, Lecce 21 February 2002 RPC readout and trigger electronics status Lecce 21/02/2002.

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Presentation on theme: "S. Veneziano, Lecce 21 February 2002 RPC readout and trigger electronics status Lecce 21/02/2002."— Presentation transcript:

1 S. Veneziano, Lecce 21 February 2002 RPC readout and trigger electronics status Lecce 21/02/2002

2 S. Veneziano, Lecce 21 February 2002 Splitter boards Small production of prototype boards done, under test: – channel boards (RN connectors) – channel boards (RG58) connectors –6 80-channel test boards (RN-LVDS-CMOS) –2 64-channel test boards (RN-LVDS-CMOS) To be mounted –6 splitter motherboards Should equip Frascati/Napoli/Tor Vergata test stands to be able to accept/reject current design, aim at December PRR (earlier production?)

3 S. Veneziano, Lecce 21 February 2002 ASIC status Wafers out second week of February, (process OK) Now under packaging Test board under construction (industrial low frequency test starts third week of March) Test vector generation 1/3 done –RAM test and functional test to be done

4 S. Veneziano, Lecce 21 February 2002 PAD board status Data trasmission test from PAD logic chip via optical transmitter to receiver OK. Working on TTC clock generation –Naples optical link bit-error-rate test OK with TTC 40 MHz clock. –Synchronous commands next (test pulse generation) need TTCVI board software Coincidence matrix board eta and phi PCBs under construction

5 S. Veneziano, Lecce 21 February 2002 Production in 2002 Our aim is to start the splitter production end of OR piggy boards (part of PAD board) production should start end of Test system (industrial standard) under construction –Test boards

6 S. Veneziano, Lecce 21 February 2002 Irradiation tests february SEE tests at Louvain –Temperature sensor –ADC –16-bit IO register –1 Mbit flash memory –OR-logic Total dose tests on these components will be done in March 3/15 components left

7 S. Veneziano, Lecce 21 February 2002 March 11th Design Reviews FDR splitter –Prototype design –Lab tests –Naples test results –Cabling document FDR PAD and optical link PDR Sector logic and ROD

8 S. Veneziano, Lecce 21 February 2002 FE output and bias circuit

9 S. Veneziano, Lecce 21 February 2002 Input pulse vs cable lenght 2 meter flat cable 10m flat cable

10 S. Veneziano, Lecce 21 February meter flat cable 10 m flat cable Receiver output vs cable lenght

11 S. Veneziano, Lecce 21 February 2002 Effect of C on pulse shape Inpad 10m 180 pf Inpad 10m

12 S. Veneziano, Lecce 21 February 2002 Input pulse shape vs Capacitance value Inpad 10m 100 pF Inpad 10m 220 pF Inpad 10m 56 pF

13 S. Veneziano, Lecce 21 February 2002 Receiver pulse width vs C 220 pF 180 pF 56 pF 100 pF

14 S. Veneziano, Lecce 21 February 2002 Pulse width vs capacitance position along cable Beginning of cable (56 pF) End of 10m cable (56 pF)

15 S. Veneziano, Lecce 21 February 2002 Input circuit simulation studies Only terminating resistor

16 S. Veneziano, Lecce 21 February 2002 Input vs output capacitance (simulation) 100 pF capacitance


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