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13 - 1 Texas Instruments Incorporated Module 13 : C28x BOOT – ROM 32-Bit-Digital Signal Controller TMS320F2812.

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Presentation on theme: "13 - 1 Texas Instruments Incorporated Module 13 : C28x BOOT – ROM 32-Bit-Digital Signal Controller TMS320F2812."— Presentation transcript:

1 Texas Instruments Incorporated Module 13 : C28x BOOT – ROM 32-Bit-Digital Signal Controller TMS320F2812

2 TMS320F2812 Memory Map MO SARAM (1K) M1 SARAM (1K) LO SARAM (4K) L1 SARAM (4K) HO SARAM (8K) Boot ROM (4K) MP/MC=0 BROM vector (32) MP/MC=0 ENPIE=0 OTP (1K) FLASH (128K) reserved PF 0 (2K) reserved PF 1 (4K) reserved PF 2 (4K) reserved PIE vector (256)ENPIE=1 XINT Zone 0 (8K)XINT Zone 1 (8K)XINT Zone 2 (0.5M) XINT Zone 6 (0.5M) XINT Zone 7 (16K) MP/MC=1 XINT Vector-RAM (32) MP/MC=1 ENPIE=0 reserved Data | Program 0x x x x00 0D00 0x x x x x x00 A000 0x3D x3D x3F x3F A000 0x3F F000 0x3F FFC0 0x3F C000 0x x x x x Data | Program 128-Bit Password reserved 0x3D 7C00

3 Reset – Boot Loader Reset OBJMODE=0 AMODE=0 ENPIE=0 VMAP=1 M0M1MAP=1 Boot determined by state of GPIO pins Reset vector fetched from boot ROM 0x3F FFC0 XMPNMC=1 (microprocessor mode) Reset vector fetched from XINTF zone 7 0x3F FFC0 XMPNMC=0 (microcomputer mode) ExecutionBootloading ExecutionBootloading Entry Point Routines FLASH SPI FLASH SPI H0 SARAM SCI-A OTPParallel load OTPParallel load Notes: F2810 XMPNMC tied low internal to device XMPNMC refers to input signal MP/MC is status bit in XINTFCNF2 register XMPNMC only sampled at reset

4 Boot Loader Options GPIO pins GPIO pins F4 F12 F3 F2 1 x x x jump to FLASH address 0x3F 7FF6 * 1 x x x jump to FLASH address 0x3F 7FF6 * jump to H0 SARAM address 0x3F 8000 * jump to H0 SARAM address 0x3F 8000 * jump to OTP address 0x3D 7800 * jump to OTP address 0x3D 7800 * 0 1 x x bootload external EEPROM to on-chip memory via SPI port 0 1 x x bootload external EEPROM to on-chip memory via SPI port bootload code to on-chip memory via SCI-A port bootload code to on-chip memory via SCI-A port bootload code to on-chip memory via GPIO port B (parallel) bootload code to on-chip memory via GPIO port B (parallel) * Boot ROM software configures the device for C28x mode before jump

5 Reset Code Flow - Summary H0 SARAM (8K) FLASH (128K) OTP (2K) 0x3F 7FF6 0x3D x3D x3F x3F F000 0x3F FFC0 Boot ROM (4K) BROM vector (32) 0x3F FC00 Boot Code     RESET Execution Entry Point Determined By GPIO Pins BootloadingRoutines (SPI, SCI-A, Parallel Load) 0x3F FC00

6 TMS320F2812 BOOT-ROM Memory Map Address Range 0x3F F000 – 0x3F F501 0x3F F502 – 0x3F F711 0x3F F712 – 0x3F F833 0x3F F834 – 0x3F F9E7 0x3F F9E8 – 0x3F FB4F 0x3F FB50 – 0x3F FBFF 0x3F FC00 – 0x3F FFBF 0x3F FFC0 – 0x3F FFC1 0x3F FFC2 – 0x3F FFFF Data & Program Space SIN/COS; 641 x 32(Q30) Normal. Inverse; 264 x 32(Q29) Normal. Sqrt;145 x32(Q30) Normal. Arctan; 218 x32(Q30) Round/Sat. 180 x 32(Q30) reserved Bootloader ; 960 x 16 RESET – Vector; 2 x 16 Int. Vectors; 62 x 16

7 C28x BOOT-ROM Vector Table Vector Address Content RESET INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INT13 INT14 DLOGINT 0x3F FFC0 0x3F FFC2 0x3F FFC4 0x3F FFC6 0x3F FFC8 0x3F FFCA 0x3F FFCC 0x3F FFCE 0x3F FFD0 0x3F FFD2 0x3F FFD4 0x3F FFD6 0x3F FFD8 0x3F FFDA 0x3F FFDC 0x3F FFDE 0x3F FC00 0x x x x x00 004A 0x00 004C 0x00 004E 0x x x x x x00 005A 0x00 005C 0x00 005E VectorRTOSINT reserved NMI ILLEGAL USER 1 USER 2 USER 3 USER 4 USER 5 USER 6 USER 7 USER 8 USER 9 USER 10 USER 11 USER 12 Address 0x3F FFE0 0x3F FFE2 0x3F FFE4 0x3F FFE6 0x3F FFE8 0x3F FFEA 0x3F FFEC 0x3F FFEE 0x3F FFF0 0x3F FFF2 0x3F FFF4 0x3F FFF6 0x3F FFF8 0x3F FFFA 0x3F FFFC 0x3F FFFE Content 0x x x x x x00 006A 0x00 006C 0x00 006E 0x x x x x x00 007A 0x00 007C 0x00 007E

8 Boot Loader Data Stream Structure 1 0x10AA : Key for memory width = 16 bit 2-9 Reserved for future use 10 Entry Point PC[22:16] 11 Entry Point PC[15:0] 12 Block Size (words); if 0 then end of transmission 13 Destination Address of block ; Addr[31:16] 14 Destination Address of block ; Addr[15:0] 15 First word of block N Last word of block N+1 Block Size (words) N+2 Destination Address of block ; Addr[31:16] N+3 Destination Address of block ; Addr[15:0]

9 Boot Loader Data Stream Example 10AA; Key for 16-Bit memory stream F; PC – starting point after load is complete: 0x3F ; 5 words in block 1 003F 9010; First block is loaded into 0x3F ; first data word ; last data 0002; Second block is two words long 003F; Second block is loaded into 0x3F ; first data 7625; last data 0000; next block zero length = end of transmission

10 C28x Boot Loader Transfer Procedure Read first word(W1) W2:W1= 0x08AA? Read BlockSize(R) Read Entry Point 16bit data size R = 0? Read BlockAddress Transfer R words from source to destination Return and Jump to Entry Point Read second word lower 8 bit W1= 0x10AA? 8bit data size Format Error No Yes

11 C28x Init Boot Function Init Boot RESET Initialize C28x: OBJMODE = 1 AMODE = 0 M0M1MAP = 1 DP = 0 OVM = 0 SPM = 0 SP = 0x Dummy Read CSM passwords Call BootModeSelect ExitBoot

12 C28x SCI Boot Loader Function C28x SCI-A Host/ e.g. PC‘s COM1 RS 232 e.g. Texas MAX232 RS 232 TxD RxD 3 2

13 C28x SCI Boot Function SCI Boot Enable SCI-A Clock Set LSPCLK to /4 Enable SCI-A Tx and Rx - Pin Setup SCI-A: 1 stop,8 data,no parity No loopback Disable SCI-A INT Disable SCI-A FIFO Prime SCI-A baud rate register Enable Autobaud detection Autobaud Lock ? Echo auto baud character Read KeyValue Valid Key? FLASH Start Boot Load Sequence No Yes

14 C28x parallel Boot Loader (GPIO) C28x GPIO Host/ e.g. PC‘s COM1 GPIO-D6 16 GPIO-B0..B15 GPIO-D5 GPIO-D6 GPIO-D : C28 indicates: “ready to receive” 2: Host signals “data active at GPIO-B” 3: C28 indicates “read is complete” 4: Host acknowledges “cycle completed” 5: C28x indicates: “ready for more data”

15 C28x GPIO Boot Function GPIO Boot Read KeyValue ( 8 or 16 Bit size) Initialize GPIO GPIO-B = input GPIO-D5 = input GPOI-D6 = output Valid Key? FLASH Call Parallel Copy Data Read Entry Point Read and discard 8 reserved words Jump Entry Point No Yes

16 Host GPIO Boot Function Start Download C28x ready? (GPIO-D6=0) Deactivate GPIO-D5 =1 Load data Signal that data avail. GPIO-D5 =0 Yes C28x ack? (GPIO-D6=1) More Data? End Download Yes No

17 C28x SPI Boot Loader Function C28x SPI Serial EEPROM DIN DOUT CLK /CS SPI - MOSI SPI - SOMI SPI - CLK GPIO – F3 ST M95080 – see Module 7 Note: (1)SPI – loader is 8bit only, it does not support 16bit data stream (2)EEPROM data stream must start at address 0x0000

18 C28x SPI Boot Loader Data Stream 1 LSB = 0xAA ( Key for 8bit transfer) 2 MSB = 0x08 ( Key for 8bit transfer) 3 LSB = LSPCLK value 4 MSB = SPIBRR value 5-18 reserved 19 Entry Point [23:16] 20 Entry Point [31:24] 21 Entry Point [7:0] 22 Entry Point [15:8] Blocks of data: block size/destination/data as shown Byte Content

19 C28x SPI Boot Function SPI - Boot Valid Key? ( 0x08AA ) Enable SPI clock Set LSPCLK to 4 No Enable SPI pin – functionality Setup SPI: 8-bit character Internal SPI-clock SPI-Master Slowest baud rate (0x7F) Relinquish from RESET Set chip enable GPIO-F3 = 1 Send Read Command To EEPROM Address = 0x0000 Read KeyValue Read LSPCLK value Requested LSPCLK = 2? Change LSPCLK FLASH C No Yes

20 C28x SPI Boot Function (cont.) Read SPIBRR value Requested SPIBRR = 0x7F? Change SPIBRR Jump EntryPoint C Yes Read 7 reserved words Read Entry Point Read Data Blocks No

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