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Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 A case study of test program generation J. M. Martins Ferreira.

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Presentation on theme: "Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 A case study of test program generation J. M. Martins Ferreira."— Presentation transcript:

1 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 A case study of test program generation J. M. Martins Ferreira FEUP / DEEC - Rua Dr. Roberto Frias Porto - PORTUGAL Tel / Fax: /

2 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)2 Objectives To present practical BS test problems through a real case study To analyse the implementation of the test protocol using the test instruction set proposed earlier To enable the student to acquire the necessary experience to develop small test programs for specific test situations To enable hands-on sessions

3 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)3 Outline The demonstration board The information required for test program generation The test vectors The test program

4 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)4 The demonstration board

5 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)5 BS infrastructure

6 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)6 Full-BS interconnects (1) Number and identification of the BS chains Is the interconnect tied to GND or V CC ? For output pins: –Number of output pins and location of the output cell, the control cell (if any) and the tristate control value For input pins: –Number of input pins and location of the input cell

7 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)7 Full-BS interconnects (2) For bidirectional pins: –Number of bidirectional pins and location of the output cell, the input cell, the control cell and the tristate control value For primary input pins: –Number of primary inputs, identification and tristate control value For primary output pins: –Number and identification of primary outputs

8 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)8 The IC1+IC2 non-BS cluster

9 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)9 Test of IC1+IC2 (1)

10 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)10 Test of IC1+IC2 (2) HILO generated 5 test vectors to provide 100% fault coverage of stuck-at pins in both components

11 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)11 The IC6 non-BS cluster

12 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)12 Test of IC6 (1)

13 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)13 Test of IC6 (2) HILO generated 5 test vectors to provide 100% fault coverage of stuck-at pins in IC6

14 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)14 The BS components

15 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)15 The test vectors A modified version of the self-diagnosis algorithm generated 6 test vectors for complete short-circuit fault detection in the 24 full-BS interconnects:

16 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)16 The serialised test vectors

17 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)17 The test program

18 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)18 Detection of open circuit X1 What are the conditions enabling the detection of open circuit X1?

19 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)19 JTAGer code (X1) start: seltap0; rst; stateirshift; ldcnt,16d;! two IRs nshf0h;! EXTEST instruction statedrshift; ldcnt,18d;! length of the BSR (IC3) nshf02000h;! /1G=0,1Y1=0,1Y2=1,1Y4=0 (in IC3) statedrshift; ldcnt,18d;! length of the BSRs ! Notice that we will shift only 18 bits, but: !- the bitstream shifted in goes to the BSR of IC3 !- the bitstream shifted out comes from the BSR of IC4 nshfcp 0h,00400h,00400h; ! check 2A3 when 1Y2=1; set 1Y2=0 jerrfaulty; statedrshift; ldcnt,18d;! length of the BSR (IC4) nshfcp 0h,0h,00400h;! check 2A3 when 1Y2=0 jerrfaulty; statereset; halt;! stop here if X1 not open faulty: statereset; halt;! stop here if X1 open

20 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)20 Detection of open circuit X1

21 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)21 Detection of short circuit X9 What are the conditions enabling the detection of X9?

22 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)22 JTAGer code (X9) start: seltap0;! the test vector is applied via TAP0 rst; stateirshift; ldcnt,8d;! length of the IR (IC3) nshf0h;! EXTEST instruction statedrshift; ldcnt,18d;! length of the BSR (IC3) nshf40000h;! /2G=0,2Y2=0,2Y3=1,2Y4=0 (in IC3) statedrselect;! test vector applied on passing UPD-DR seltap1;! response capturing is via TAP1 rst; stateirshift; ldcnt,8d;! length of the IR (IC5) nshf0h;! EXTEST instruction statedrshift;! test response captured on passing CAPT-DR ldcnt,18d;! length of the BSR (IC5) nshfcp 0h,00400h,00400h; ! check if 2A2,2A3,2A4 are 0,1,0 jerrfaulty; statereset; halt;! stop here if X9 is not shorted faulty: statereset; halt;! stop here if X9 is shorted

23 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)23 Detection of short circuit X9

24 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)24 Detection of short circuit X9

25 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)25 Detection of short circuit X16 What are the conditions enabling the detection of X16?

26 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)26 JTAGer code (X16) start: seltap0; rst; stateirshift; ldcnt,16d;! length of the IRs (IC3,IC4) nshfcp 0h,8080h,8080h; jerrfaulty; statereset; halt;! stop here if X16 is not shorted faulty: statereset; halt;! stop here if X16 is shorted

27 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)27 Detection of short circuit X16

28 Leonardo da Vinci ALLEGRO © J. M. Martins Ferreira - University of Porto (FEUP / DEEC)28 Detection of short circuit X16 What would happen if only the first 8 bits were shifted out? (instead of 16) ldcnt,8d;! length of the IR (IC4) nshfcp0h,80h,80h;


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